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features ? audio codec ? 100db dynamic range stereo audio dac - 8 to 96 khz sampling frequency ? 96db dynamic range stereo audio adc - 8 to 96 khz sampling frequency ? 16 / 32 ohms headset amplifier with capless operation ? snr: 97 db a-weighted ? thd: -60 db (16ohms / 20mw / 3.3v supply) ? maximum output power: 55mw (16ohms / 3.3v supply) ? stereo line inputs, stereo auxiliary inputs ? stereo microphone inputs with bias generator for electret device ? low power analog bypass mode (line / aux in to headset out) ? low power analog sidetone mode (microphone in to headset out) ? automatic audio path control with smooth fade in / fade out operation ?i 2 s port ? master / slave operation ?i 2 s / left / right justified modes ? 16 / 18 / 20 / 24 bit operation ? 6x supply channel voltage regulators ? dcdc0: ? 1.85v - 600ma. 0.8 to 3.6v / 50mv step. ? 2 mhz switching buck regulator ? fast load transient response - pwm / pfm modes. ? efficiency up to 92% ? dcdc1: ? 1.2v - 600ma. 0.8 to 3.6v / 50mv step. ? 2 mhz switching buck regulator ? fast load transient response - pwm / pfm modes. ? efficiency up to 90% ? ldo2: 1v - 300ma. 0.8 to 1.35v / 50mv step - fast transient response ? ldo3: 3.3v - 200ma. 2.7 to 3.6v / 50mv step - fast transient response ? ldo4: 3.3v - 200ma. 2.7 to 3.6v / 50mv step - audio codec supply ? ldo5: 2.5v - 10ma - backup battery charger and rtc supply ? low consumption power manager ? 2.5v - 5.5v vin operation ? 20ua typical consumption off mode ? vin monitor, cpu supplies monitor ? die temperatue and over-current protections ? reset and interrupt generation ? automatic voltage ramping on supp ly channels for dvs applications ? standby mode with selectable supplies off ? rtc ? ultra low power crystal oscillator (<1ua typ.) ? wake up function with programmable alarm or selectable inputs ? 10-b / 300ks/s adc with 4 external / 6 int\ernal selectable inputs ? two-wire interface for pmu and audio controls ? available in 7.5 x 7.5 x 0.9 mm 64-pin qfn package ? applications: multimedia , audio + supply solution for mpu+ddr2 designs. power management and analog companions (pmaac) AT73C246 6 supply channel pmu with audio codec 11050a?pmaac?07-apr-10
2 11050a?pmaac?07-apr-10 AT73C246 1. description the AT73C246 is an integrated high performance power management and audio ic. it is specif- ically designed for advanced technology applicat ion processors with complex and low voltage supplies targeting audio applications from low to high end. this system-on-chip allows signifi- cant savings in both cost and board area over previous discrete solutions. directly operated from a 2.9v to 5.5v input voltage, the pmu generates a set of 4 regulated power supplies and an associated delayed reset signal. these 4 voltages are built up with 2 high efficiency dcdc buck converters and 2 low noise ldos. featuring ultra fast transient responses and integrating automatic voltage scaling function , these supplies perfectly fit with modern low voltage mcu cores and memory supplies (ddr , flash, ...). an additional 200ma ldo under software control is provided for auxiliary application functions . the high performances of this ldo (high psrr, low noise, fast transient response) makes it ideal for analog front-ends (audio, rf...) as well digital peripherals. aside from the pmu, the AT73C246 integrates a complete state-of-the art low power audio codec with headphone amplifier. on the input si de, a stereo microphone preamplifier with differ- ential or single ended connection (micdiff / mic) and 2 selectable stereo inputs (line / aux) are directed to a 96db dynamic range stereo aud io adc through an input mixer. on the output side a 100db dynamic range stereo audio dac drives, through an output mixer, a 60 mw stereo headphone amplifier which comes along with a vcm buffer. this vcm buffer allows to save two large on-board coupling capacitors for area cons trained applications. additionally two fully ana- log paths called bypass and sidetone from line / aux and microphone inputs to headphone outputs allow to reduce the audio power consumption to minimum when needed. the pmu is complemented with a low power rtc system including a recharging ldo, a crystal oscillator and a programmable alarm that is fully integrated in the pmu digital core. thus, the rtc function is able to wake up the pmu, i.e the regulated power supplies, at a programmed instant. also, a 10-bit adc equipped with a 10:1 analog mu ltiplexer is provided to the application to per- form voltage measurements. finally, to reduce power consumption to minimu m, the pmu features a flexible standby mode where the mcu is placed in reset state with se lectable supplies on, off or in low-power mode. power consumption in off mode is typically 20ua.
3 11050a?pmaac?07-apr-10 AT73C246 2. block diagram figure 2-1. AT73C246 functional block diagram ldo4 3.3v (codec) audio codec digital core vin4 vin0 sw0 vfb0 gnd0 buck0 1.8v max: 600ma (core + mem) twd twck max: 200ma vdd4 avdd vin1 sw1 vfb1 gnd1 buck1 1.2v max: 600ma (core) vin2 ldo2 1v max: 300ma (core) vdd2 vin3 ldo3 3.3v max: 200ma (i/o) vdd3 vinsys ldo5 2.5v max: 10ma (backup) vbackup ldo6 1.8v / 10ma vddc vmid micbias agnd audio bias linr linl micl audio in + adc auxr auxl hpdet hpl hpr hpvcm audio out + dac mclk lrfs bclk dai audio port dao xin clk32k xout wakeup0 rtc + osc pmu bias rext vbg gndsys ana0 analog mux ana1 ana2 ana3 10b sar adc pmu state machines rstb itb vpad dgnd twi dcdc 4mhz rc oscillator wakeup1 wakeup2 wakeup3 hrst pwren vbackup die temp sensor system 32khz rc oscillator micln micr micrn led internal voltages 37 36 28 27 30 29 34 31 33 32 18 35 12 17 13 14 16 15 44 43 42 41 40 63 64 49 62 60 61 3 4 5 6 22 21 26 nc 47 nc 48 nc 2 65 45 25 24 23 19 20 11 9 10 8 7 1 39 38 50 51 55 52 54 53 59 56 58 57 nc 46 (internal functions)
4 11050a?pmaac?07-apr-10 AT73C246 3. package and pinout figure 3-1. AT73C246 qfn64 package pinout - top view 1 16 17 32 33 48 49 64 vbackup led ana0 ana1 ana2 ana3 vinsys vddc vbg rext gndsys vmid hpdet hpr hpvcm hpl agnd avdd itb rstb twd twck wakeup1 wakeup2 wakeup3 nc linr linl auxr auxl micln micrn nc nc nc vpad mclk lrfs bclk dai dao vdd3 vin3 vin4 vdd4 micbias micl micr xout xin wakeup0 pwren hrst gnd0 sw0 vin0 vfb0 gnd1 sw1 vin1 vfb1 vin2 vdd2 mclk32
5 11050a?pmaac?07-apr-10 AT73C246 4. pin description table 4-1. pin description pin name i/o pin number type function vbackup output 1 analog rtc supply led output 2 digital output for blinking led. leave not connected if a led is not wired. ana0 input 3 analog measurement input 0 ana1 input 4 analog measurement input 1 ana2 input 5 analog measurement input 2 ana3 input 6 analog measurement input 3 vinsys input 7 power pmu core supply vddc output 8 analog pmu / audio digital supply. internal use only. no resistive load. vbg output 9 analog pmu voltage reference rext output 10 analog resistor connection for pmu bias current gndsys gnd 11 analog pmu ground vmid output 12 analog audio codec mid-supply reference hpdet input 13 analog headset detector hpr output 14 analog headset output right hpvcm output 15 analog headset virtual ground output hpl output 16 analog headset output left agnd gnd 17 analog audio codec ground avdd input 18 power audio codec supply input itb output 19 digital interrupt request - active low - open- drain rstb output 20 digital cpu reset - active low - open drain twd input/output 21 digital two wire interface - data twck input 22 digital two wire interface - clock wakeup1 input 23 digital wake up 1 input - vpad level - 100k pull down wakeup2 input 24 digital wake up 2 input - vpad level - 100k pull down wakeup3 input 25 digital wake up 3 input - vpad level - 100k pull down nc - 26 - connect to dgnd linr input 27 analog audio line input right linl input 28 analog audio line input left auxr input 29 analog audio auxiliary input right auxl input 30 analog audio auxiliary input left
6 11050a?pmaac?07-apr-10 AT73C246 micln input 31 analog audio negative microphone input left micrn input 32 analog audio negative microphone input right micr input 33 analog audio positive microphone input right micl input 34 analog audio positive microphone input left micbias output 35 analog voltage bias for electret microphone vdd4 output 36 power ldo4 output - 3.3v typ vin4 input 37 analog ldo4 input vin3 input 38 power ldo3 input vdd3 output 39 analog ldo3 output - 3.3v typ dao output 40 digital digital audio port data output dai input 41 digital digital audio port data input bclk input/output 42 digital digital audio port bit clock lrfs input/output 43 digital digital audio port left/right clock mclk input 44 digital audio codec master clock input vpad input 45 power pmu i/o ring supply nc - 46 - leave open nc - 47 - connect to dgnd nc - 48 - connect to dgnd mclk32 output 49 digital rtc clock output - vpad level vdd2 output 50 analog ldo2 output vin2 input 51 power ldo2 input vfb1 input 52 analog dcdc1 voltage feedback input vin1 input 53 power dcdc1 power stage supply sw1 output 54 analog dcdc1 power stage output gnd1 ground 55 analog dcdc1 power stage ground vfb0 input 56 analog dcdc0 voltage feedback input vin0 input 57 analog dcdc0 power stage supply sw0 output 58 analog dcdc0 power stage output gnd0 ground 59 analog dcdc0 power stage ground hrst input 60 digital hard reset - vbackup level - 100k pull down pwren input 61 digital power on/off - vbackup level - 100k pull down wakeup0 input 62 digital wake up 0 input - vbackup level - 100k pull down table 4-1. pin description pin name i/o pin number type function
7 11050a?pmaac?07-apr-10 AT73C246 xin input 63 analog rtc crystal oscillator input xout output 64 analog rtc crystal oscillator output dgnd ground 65 analog pmu digital ground + thermal pad. table 4-1. pin description pin name i/o pin number type function
8 11050a?pmaac?07-apr-10 AT73C246 5. application block diagram figure 5-1. AT73C246 application block diagram ldo4 3.3v (codec) vin c41 audio codec digital core vin4 vin vin0 sw0 vfb0 gnd0 vdd0 buck0 1.8v max: 600ma 2.2h (core + mem) twd twck max: 200ma vdd4 c1 10f c42 10f 10f avdd vin vin1 sw1 vfb1 gnd1 vdd1 buck1 1.2v max: 600ma 2.2h c4 22f (core) c3 10f vdd0 vin2 ldo2 1v c6 10f c5 2.2f max: 300ma (core) vdd2 c2 22f vin vin3 ldo3 3.3v c8 10f c7 10f max: 200ma (i/o) vdd3 vinsys vinsys ldo5 2.5v c9 2.2f c10 2.2f max: 10ma (backup) vbackup + 2k backup battery ldo6 1.8v / 10ma c11 2.2f (internal functions) vddc vmid c23 1f vdd4 micbias agnd audio bias linr linl micl audio in + adc 3.3f 100k 100k 3.3f c40 1nf c38 1nf linejack auxr auxl 3.3f 100k 100k 3.3f c36 1nf c34 1nf auxjack 1f c32 1nf mic_l 2k headset 32ohms hpdet hpl hpr hpvcm audio out +dac c21 3.3f 100k c22 3.3f 100k 100 100 100 100 100 lineout 100 mclk lrfs bclk dai audio port dao i2s to mcu xin clk32k xout wakeup0 rtc + osc c2 0 12p c1 9 12 p vbackup pmu bias rext 560k 1% c12 22nf vbg gndsys ana0 analog inputs c15 22nf 100 ana_0 ana1 c16 22nf 100 ana_1 ana2 c17 22nf 100 ana_2 ana3 c18 22nf 100 ana_3 10b sar adc pushbutton pmu state machines rstb c13 10nf 4.7k vdd0/vdd3 itb c14 10nf 4.7k vdd0/vdd3 vpad led twi dcdc 4mhz rc oscillator 4.7k vdd0/vdd3 4.7k vdd0/vdd3 twd twck to mcu twi wakeup1 wakeup2 wakeup3 from mcu pushbutton hrst pushbutton pwren vbackup die temp sensor system 32khz rc oscillator micln 1f c30 1nf micr 1f c28 1nf mic_r 2k micrn 1f c26 1nf dgnd vin 470 vbackup vbackup 100k 2k 2k 100k 100k 100k 100k 100k l1 l2 r1 bat 1 r2 r3 r4 r5 d1 r6 r7 r11 r10 r9 r8 s1 s2 s3 r12 r13 r14 r15 r18 r19 r22 r23 r24 r25 r27 r26 r28 r29 r31 r30 c25 c27 c29 c31 c33 c35 c37 c39 x1 j1 j2 j3 j4 j5 j6 vdd0/vdd3 57 58 56 59 53 54 52 55 51 50 38 39 1 7 8 10 9 11 20 19 23 24 25 45 2 65 37 36 28 27 30 29 34 31 33 32 18 35 12 17 13 14 16 15 44 43 42 41 40 63 64 49 62 60 61 3 4 5 6 22 21 26 47 48 nc 46
9 11050a?pmaac?07-apr-10 AT73C246 table 5-1. typical application components design schematic reference value description r1, r18, r19, r22, r23 2k 5% / 0.063w r2 560k 1% / 0.063w r3, r4, r6,r7 4.7k 5% / 0.063w r5 470 5% / 0.063w r8, r9, r10, r11, r14, r15, r26, r27, r30, r31 100 5% / 0.063w r12, r13, r24, r25, r28, r29 100k 5% / 0.063w c1, c3, c6, c7, c8, c10, c41, c42 10f x5r / 6.3v tdk: c1608x5r0j106mt murata: grm188r60j106me47 c2, c4 22f x5r / 6.3v tdk: c2012x5r0j226m murata: grm21br60j226me39 c5, c9, c11 2.2f x5r / 6.3v c23, c25, c27, c29, c31 1f x5r / 6.3v c13, c14 10nf x5r / 6.3v c15, c16, c17, c18, c12 22nf x5r / 6.3v c19, c20 12pf c0g / 25v c21, c22, c33, c35, c37, c39 3.3f x5r / 6.3v c26, c28, c30, c32, c34, c36, c38, c40 1nf x5r l1, l2 2.2h coilcraft: lps3314-222
10 11050a?pmaac?07-apr-10 AT73C246
11 11050a?pmaac?07-apr-10 AT73C246 6. absolute maximum ratings notes: 1. refer to power dissipation rating section 2. according to specifications mil-883 -method 3015.7 (hbm - human body model) / jesd22 a115 (mm - machine model) 7. recommended operating conditions note: 1. refer to power di ssipation rating section 8. power dissipation ratings note: 1. according to specification jesd51-5 table 6-1. absolute maximum ratings operating temperature (industrial).................-40 c to + 85 ? c (1) *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational se ctions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reli- ability. storage temperature......................................-55c to + 150c power supply input on v insys , v in{0,1,3,4}, v pad .. -0.3v to + 5.5v power supply input on v in2 , a vdd ...................... -0.3v to + 3.6v digital i/o input voltage...................................... -0.3v to + 5.5v all other pins.......................................................-0.3v to + 5.5v esd (all pins).........................................2 kv hbm / 100v mm (2) table 7-1. recommended operating conditions parameter condition min max units operating ambiant temperature (1) -40 85 c power supply input v insys 2.5 5.5 v power supply input v in{0,1,3,4} 2.9 5.5 v power supply input v in2 1.65 3.6 v power supply input a vdd 2.7 3.6 v power supply input v pad 1.75 5.5 v table 8-1. recommended operating conditions parameter condition min typ max units junction temperature (tj) -40 125 c r thja (1) package thermal junction to ambient resistance 30 35 c / w maximum on-chip power dissipation ambient temperature = 70c 1.8 1.6 w ambient temperature = 85c 1.3 1.1 w
12 11050a?pmaac?07-apr-10 AT73C246 9. pmu electrical characteristics 9.1 current consumption versus modes 9.2 supply monitor thresholds the following table applies to functional stat e diagrams of figure 11-1 ?AT73C246 power man- ager functional state diagram? on page 25 and figure 11-2 ?AT73C246 start-up and shutdown state diagram? on page 26 . table 9-1. current consumption versus modes symbol parameter comments min typ max units v in operating supply voltage v insys, v in{0,1,3,4} present. 2.9 3.6 5.5 v i dd_vin powerdown mode. all ldos and dcdc converters off. audio off. rtc running. -2040a run mode. all ldos and dcdc converters running in pwm. audio off. rtc running. -715ma standby mode. default setup: dcdc0 on in low- power mode. ldo3 on. all other functions off. -310500a i dd_rtc all modes. rtc running. total current entering pin v backup 15a table 9-2. supply monitor thresholds symbol parameter comments min typ max units v in > 3.1v pmu input 3.1v risi ng threshold 3.070 3.1 3.130 v v in < 2.9v pmu input 2.9v falli ng threshold 2.870 2.9 2.930 v v in > 2.7v pmu input 2.7v rising threshold 2.70 2.75 2.85 v v in < 2.7v pmu input 2.7v falling threshold 2.60 2.65 2.70 v v bkp > 1.8v v backup input rising threshold 1.80 1.85 1.90 v v bkp < 1.8v v backup input falling threshold 1.70 1.75 1.80 v
13 11050a?pmaac?07-apr-10 AT73C246 9.3 digital i/os dc characteristics notes: 1. v pad referred pins itb, rstb: open drain outputs. only v ol and i o parameters are applicable. 2. v pad referred pins wakeup1, wakeup2, wakeup3 , mclk, dai, twck: cmos inputs. only v ih and v il parameters are applicable. 3. v pad referred pins mclk32k, dao: cmos outputs. only v ol , v oh and i o parameters are applicable. 4. v pad referred pin twd: cmos input and open drain output. only v il , v ih , v ol , i o parameters are applicable. 5. v pad referred pins lrfs, bclk: cmos bidir. all parameters applicable note: v backup referred pins pwren, hrst, wakeup0: cmos inputs. only v il and v ih parameters are applicable. table 9-3. v pad referred digital i/os symbol parameter comments min typ max units v pad operating supply voltage 1.75 3.6 5.5 v v il input low-level voltage -0.3 - 0.3 x v pad v v ih input high-level voltage 0.7 x v pad - v pad + 0.3 v v oh output high-level voltage i o max. 0.75 x v pad --v v ol output low-level voltage i o max - - 0.25 x v pad v i o output current - - 8 ma r p pull-up or pull-down resistance when applicable. 70 100 145 k table 9-4. v backup referred digital i/os symbol parameter comments min typ max units v backup operating supply voltage 1.75 2.5 2.65 v v il input low-level voltage -0.3 - 0.3 x v backup v v ih input high-level voltage 0.7 x v backup - v backup + 0.3 v v oh output high-level voltage i o max. 0.75 x v backup --v v ol output low-level voltage i o max - - 0.25 x v backup v i o output current - - 8 ma r p pull-up or pull-down resistance when applicable. 70 100 145 k
14 11050a?pmaac?07-apr-10 AT73C246 9.4 dcdc0 and dcdc1 unless otherwise specified: external components l=2.2 h, c out =22 f and c in =10 f. v in{0,1} > v dd{0,1} + 500mv. t j = [-40c ; +125c]. table 9-5. dcdc0 and dcdc1 electrical characteristics symbol parameter comments min typ max units v in operating supply voltage v in0 , v in1 and v insys 2.9 3.6 5.5 v i dd supply current (1) off - - 1 a pfm operation. v dd0 = 1.85v, v dd1 = 1.2v - 40 80 a pwm operation. v dd0 = 1.85v, v dd1 = 1.2v - 36.5ma i o output current pfm operation. - - 50 ma pwm operation. - - 600 ma f sw switching frequency pwm operation. 1.8 2 2.2 mhz v dd0 default output voltage (2) v dd0 -1.85- v v dd1 v dd1 -1.2- v v dd_range programmable output voltage range pfm or pwm operation. 0.8 3.6 v v dd_step output voltage steps pfm or pwm operation. 50 mv n step number of output steps in case of direct output voltage programming. auto matic ramping not active. 4 step / 100s t step step time with automatic ramping. 260 280 300 s v dd_acc dc output voltage accuracy pfm; t j = 25c ; i o = 0 ma -1.5 2.5 % pfm; t j = [-40;125c] ; i o = 0 ma -2 3 pwm; t j = 25c ; i o = 0 ma -1.5 1.5 pwm; t j = [-40;125c] ; i o = 0 ma -2 2 v dd_ripple ripple voltage pwm operation. 2 mv vdd_il static load regulation pwm operation. i o ranging from 0 to i omax 25mv dynamic load regulation pwm. i o : 0 to i omax ; 1 s rise time -40 mv pwm. i o : i omax to 0 ; 1 s fall time 40 vdd_vin static line regulation v in0 and v insys from 2.9 to 5.5v v dd0 = 1.85v, v dd1 = 1.2v 5mv eff efficiency pwm. i omax load. v dd0 = 1.85v. relative to v in0 input supply. 85 % pwm. i omax load. v dd1 = 1.2v. relative to v in1 input supply. 78 % i inrush inrush current (1) current from v in(0,1) and v insys from 0 to 100% v dd{0,1} v dd0 = 1.85v, v dd1 = 1.2v 30 200 ma
15 11050a?pmaac?07-apr-10 AT73C246 notes: 1. current consumption without load . one dcdc converter on, the other one off. 2. default output voltage are set during manufacturing. please contact atmel for other default settings. 3. threshold levels are programmed in register pmu_rst_lvl (0x04) ocp over-current protection output current. 1 1.4 1.8 a t start start-up time from off to pwm operation. v dd(0,1) rising to 95% of final value. 5ms t pwm pfm to pwm settling time no output load. 10 s pwrf det power fail detector threshold accuracy overload of the programmed threshold by 10mv / 5us min (3) . -1 - +1 %.v dd c out total capacitive load at v fb{0,1} pins. 8 36 f table 9-5. dcdc0 and dcdc1 electrical characteristics symbol parameter comments min typ max units
16 11050a?pmaac?07-apr-10 AT73C246 9.5 ldo2 unless otherwise specified: external components c out =10 f, c in =10 f, t j = [-40c ; +125c]. notes: 1. current consumption in v in2 without load. 2. default output voltage are set during manufacturing. please contact atmel for other default settings. 3. threshold level is programmed in register pmu_rst_lvl (0x04) 4. v dropout = v in2 - v dd2 when v dd2 = 98% of v dd2 obtained with v in2 > v dd2 + 500mv table 9-6. ldo2 electrical characteristics symbol parameter comments min typ max units v in operating supply voltage v in2 1.65 1.8 3.6 v i dd supply current (1) off - - 1 a on - - 250 a i o output current v in2 > v dd2 + 500mv. - - 300 ma v dd2 default output voltage (2) -1-v v dd_range programmable output voltage range 0.8 1.35 v v dd_step output voltage steps 50 mv t step step time with automatic ramping. 570 600 630 s v dd_acc dc output voltage accuracy v in2 > v dd2 + 500mv t j = 25c ; i o = 0 ma -1 1 % v in2 > v dd2 + 500mv t j = [-40c ; 125c] ; i o = 0 ma -1.5 1.5 vdd_il static load regulation v in2 > v dd2 + 500mv i o ranging from 0 to i omax 0.05 1 %.v dd2 dynamic load regulation v in2 > v dd2 + 500mv i o: 0 to i omax ; 1 s rise time -50 mv v in2 > v dd2 + 500mv i o: i omax to 0 ; 1 s fall time 50 vdd_vin static line regulation i o = 0 ma v in2 from 1.65 to 3.6v 5mv v dropout drop out voltage (4) i o = 200ma 300 mv i o = 300ma 450 mv i inrush inrush current current from v in2 from 0 to 95% of final value. 200 500 ma t start start-up time v dd2 off and rising to 95% of final value. i o = 0 ma 1ms pwrf det power fail detector threshold accuracy overload of the programmed threshold by 10mv / 5us min (3) . -1 - +1 %.v dd2
17 11050a?pmaac?07-apr-10 AT73C246 9.6 ldo3 unless otherwise specified: external components c out =10 f, c in =10 f, t j = [-40c ; +125c]. notes: 1. current consumption in v in3 without load. 2. default output voltage are set during manufacturing. please contact atmel for other default settings. 3. threshold level is programmed in register pmu_rst_lvl (0x04) 4. v dropout = v in3 - v dd3 when v dd3 = 98% of v dd3 obtained with v in3 > v dd3 + 300mv table 9-7. ldo3 electrical characteristics symbol parameter comments min typ max units v in operating supply voltage v in3 2.9 3.6 5.5 v i dd supply current (1) off - - 1 a on - - 350 a i o output current v in3 > v dd3 + 300mv. - - 200 ma v dd3 default output voltage (2) -3.3- v v dd_range programmable output voltage range 2.7 3.6 v v dd_step output voltage steps 50 mv t step step time with automatic ramping. 570 600 630 s v dd_acc dc output voltage accuracy v in3 > v dd3 + 300mv t j = 25c ; i o = 0 ma -1 1 % v in3 > v dd3 + 300mv t j = [-40c ; 125c] ; i o = 0 ma -1.5 1.5 vdd_il static load regulation v in3 > v dd3 + 300mv i o ranging from 0 to i omax 0.05 0.5 %.v dd3 dynamic load regulation v in3 > v dd3 + 300mv i o: 0 to i omax ; 1 s rise time -40 mv v in3 > v dd3 + 300mv i o: i omax to 0 ; 1 s fall time 40 vdd_vin static line regulation v in3 > v dd3 + 300mv. i o = 0 ma v in3 from 2.9 to 5.5v 5mv v dropout drop out voltage (4) i o = 10ma 50 mv i o = 200ma 250 mv psrr power supply rejection ratio v in3 > v dd3 + 300mv i o = 1ma. dc to 3khz. 60 db v in3 > v dd3 + 300mv i o = 10ma. dc to 3khz. 50 i inrush inrush current current from v in3 from 0 to 95% of final value. 200 500 ma t start start-up time v dd3 off and rising to 95% of final value. i o = 0 ma 1ms pwrf det power fail detector threshold accuracy overload of the programmed threshold by 10mv / 5us min (3) . -1 - +1 %.v dd3
18 11050a?pmaac?07-apr-10 AT73C246 9.7 ldo4 unless otherwise specified: external components c out =10 f, c in =10 f, t j = [-40c ; +125c]. notes: 1. current consumption in v in4 without load. 2. default output voltage are set during manufacturing. please contact atmel for other default settings. 3. v dropout = v in4 - v dd4 when v dd4 = 98% of v dd4 obtained with v in4 > v dd4 + 300mv table 9-8. ldo4 electrical characteristics symbol parameter comments min typ max units v in operating supply voltage v in4 2.9 3.6 5.5 v i dd supply current (1) off - - 1 a on - - 350 a i o output current v in4 > v dd4 + 300mv. - - 200 ma v dd4 default output voltage (2) -3.3- v v dd_range programmable output voltage range 2.7 3.6 v v dd_step output voltage steps 50 mv t step step time with automatic ramping. 570 600 630 s v dd_acc dc output voltage accuracy v in4 > v dd4 + 300mv t j = 25c ; i o = 0 ma -1 1 % v in4 > v dd4 + 300mv t j = [-40c ; 125c] ; i o = 0 ma -1.5 1.5 vdd_il static load regulation v in4 > v dd4 + 300mv i o ranging from 0 to i omax 0.05 0.5 %.v dd4 dynamic load regulation v in4 > v dd4 + 300mv i o: 0 to i omax ; 1 s rise time -40 mv v in4 > v dd4 + 300mv i o: i omax to 0 ; 1 s fall time 40 vdd_vin static line regulation v in4 > v dd4 + 300mv. i o = 0 ma v in4 from 2.9 to 5.5v 5mv v dropout drop out voltage (3) i o = 10ma 50 mv i o = 200ma 250 mv psrr power supply rejection ratio v in4 > v dd4 + 300mv i o = 1ma. dc to 3khz. 60 db v in4 > v dd4 + 300mv i o = 10ma. dc to 3khz. 50 i inrush inrush current current from v in4 from 0 to 95% of final value. 200 500 ma t start start-up time v dd4 off and rising to 95% of final value. i o = 0 ma 1ms
19 11050a?pmaac?07-apr-10 AT73C246 9.8 ldo5 unless otherwise specified: external components c out =2.2 f, c in =10 f, t j = [-40c ; +125c]. note: 1. current consumption in v insys without plugged backup battery table 9-9. ldo5 electrical characteristics symbol parameter comments min typ max units v in operating supply voltage v insys 2.7 3.6 5.5 v i dd supply current (1) off - - 1 a on - - 7 a i o output current - - 10 ma v backup output voltage accuracy 2.42 2.5 2.58 v vdd_vin static line regulation v insys from 2.7 to 5.5v 3 10 mv vdd_vin static line regulation v insys =3.6v, i o from 0 to i omax 10 15 mv i inrush inrush current current from v insys from 0 to t start(max) . v backup = 2.5v 180 350 ma t start start-up time v backup off and rising to 95% of final value. 1ms
20 11050a?pmaac?07-apr-10 AT73C246 9.9 measurement bridge and 10-bit adc notes: 1. the 10-bit adc is supplied from the regulated v ddc voltage (1.8v) which is generated from v insys . 2. please refer to atmel data converter terminology literature table 9-10. measurement bridge and 10-bit a dc electrical characteristics symbol parameter comments min typ max units v in operating supply voltage (1) v insys 2.9 3.6 5.5 v i dd supply current off - - 1 a on - - 2 ma v ref reference voltage internally connected to vddc pin. 1.75 1.8 1.85 v inl integral non linearity end point method -2 - +2 lsb dnl differential non linearity end point method -1 - +1 lsb offset offset error -2 +2 lsb gain gain error -2 +2 lsb f s sampling rate 300 ks/s t acq track and hold acquisition time 500 ns v meas measured input voltage range external inputs ana{0,1,2,3} 0.4 v insys v v dd{0,1,2,3,4} inputs 0.4 4 v v insys input 0.4 5.5 v att meas measured input scaling factor external inputs ana{0,1,2,3} -1% 0.25 +1% v/v v dd{0,1,2,3,4,5} inputs -1% 0.4 +1% v/v v insys input -1% 0.25 +1% v/v r in_nom ana{0,1,2,3} input resistance t j = 25c 96 120 144 k r in_temp r in deviation with temperature t j [-40 ; +25]. relative to r in_nom + 20 % t j [25 ; 125]. relative to r in_nom -16 c in ana{0,1,2,3} input capacitance 15 pf
21 11050a?pmaac?07-apr-10 AT73C246 9.10 rtc crystal oscillator note: 1. current consumption in v backup with crystal. in case of crystal not present on-board, back-up batteries or supercapacitors, must be avoided. 9.11 die temperature sensor table 9-11. rtc crystal oscillator elec trical characteristics symbol parameter comments min typ max units v in operating supply voltage v backup 1.75 2.5 2.65 v freq frequency with crystal - 32.768 - khz duty duty cycle 40 50 60 % i dd supply current (1) off - - 5 na on - - 1.5 a t on startup time c l = 12pf - 1000 1500 ms v xin level sinus wave on xin 250 300 mvpp v xout vpp on xout 300 mvpp r f internal resistor between xin and xout 10 m drift accuracy @25c, +/- 20ppm 1.5 mn/month esr equivalent series resistance rs crystal @ 32.768khz 50 100 k c m motional capacitance crystal @ 32.768khz 0.6 3 ff c shunt shunt capacitance crystal @ 32.768khz 0.6 2 pf c load load capacitance crystal @ 32.768khz 6 12.5 pf table 9-12. die temperature sensor electrical characteristics symbol parameter comments min typ max units t shutdown 130c shutdown threshold 135 145 155 c t restart 110c restart threshold 105 115 125 c
22 11050a?pmaac?07-apr-10 AT73C246 10. audio codec elect rical characteristics unless otherwise specified: avdd = 3.3v, t a = 25c, mclk = 12.288mhz, f s = 48khz. master mode and 24-bit operation on i 2 s port. all gains set to 0db, audio effe cts are off. noise measurements are made in the [20hz-20khz] band using the a-weighting filter. distortion measurements are made from the 2 nd to the 5 th harmonic products of a 997hz input sinewave. input sources have an internal impedance of 50 ohms. au dio path without mixing capability. table 10-1. audio codec bias symbol parameter comments min typ max units avdd operating supply voltage 2.7 3.3 3.6 v i dd supply current off 20 a standby 1 ma v mid mid-supply reference voltage -1% avdd / 2 +1% v t mid_on time to charge v mid capacitor from 0 to 95% of final value 350 ms/ f t mid_off time to discharge v mid capacitor from 0 to 95% of final value 700 ms/ f v micbias microphone bias reference voltage no load. avdd v r micbias microphone bias reference voltage internal resistance 1.5 1.9 2.3 k table 10-2. line record path: line or auxiliary input to adc output symbol parameter comments min typ max units v fs full scale input voltage (1) corresponds to 0dbfs digital output signal. avdd / 3.3 v rms snr signal-to-noise ratio (2) avdd = 3.3v 85 96 - db avdd = 2.7v 82 93 - db dr dynamic range (3) avdd = 3.3v 85 96 - db avdd = 2.7v 82 93 - db thd total harmonic distortion -1dbfs digital output - -80 -74 db xtalk left / right channel separation (5) 80 90 - db g line programmable gain range -34 0 12 db gain step size - 1 - db mute attenuation (6) 80 - - db r in input resistance 5.9 7 8.1 k c in input capacitance - - 10 pf table 10-3. microphone record path: microphone input to adc output symbol parameter comments min typ max units v fs full scale input voltage (1) corresponds to 0dbfs digital output signal. avdd / 3.3 v rms snr signal-to-noise ratio (2) avdd = 3.3v 85 96 - db avdd = 2.7v 82 93 - db
23 11050a?pmaac?07-apr-10 AT73C246 dr dynamic range (3) avdd = 3.3v 85 96 - db avdd = 2.7v 82 93 - db thd total harmonic distortion -1dbfs digital output - -84 -74 db xtalk left / right channel separation (5) 80 90 - db g line programmable gain range 0 - 46 db gain step size - 1 - db mute attenuation (6) 80 - - db r in input resistance 0db gain 8.4 12 15.6 k c in input capacitance - - 10 pf table 10-4. playback path: dac input to headphone output symbol parameter comments min typ max units v fs full scale output voltage (1) 0dbfs digital input signal. avdd / 3.3 v rms snr signal-to-noise ratio (2) avdd = 3.3v 92 97 - db avdd = 2.7v 89 94 - db dr dynamic range (3) avdd = 3.3v 92 97 - db avdd = 2.7v 89 94 - db thd total harmonic distortion 0dbfs input - 10k load - -88 -80 db 20mw output - 32 load - -65 -60 db 20mw output - 16 load - -60 -55 db p o output power 32 load - thd < -40db or 1% 30 mw 16 load - thd < -40db or 1% 50 mw xtalk left / right channel separation (5) 10k ac coupled load 90 db 16 dc coupled load 60 db g hs programmable gain range -77 - +6 db gain step size - 1 - db mute attenuation (6) 80 - - db table 10-5. analog bypass path: line / aux iliary input to headphone output symbol parameter comments min typ max units v fs full scale output voltage (1) avdd / 3.3 v rms snr signal-to-noise ratio (2) avdd = 3.3v 92 97 - db avdd = 2.7v 89 94 - db dr dynamic range (3) avdd = 3.3v 92 97 - db avdd = 2.7v 89 94 - db table 10-3. microphone record path: microphone input to adc output symbol parameter comments min typ max units
24 11050a?pmaac?07-apr-10 AT73C246 notes: 1. full scale: a linear extrapolation to 0dbfs of the measured level at -10dbfs. 2. signal-to-noise ratio: the ratio of the rms value of a 997hz full scale sine wave to the rms value of output noise with no signal applied. device is not muted. 3. dynamic range: according to aes17-1991 (audio engineering society) and eiaj cp-307 (electronic industries associa- tion of japan), an extrapolation to 0dbfs input signal of t he thd+n ratio measurement at -60dbfs. as an example, if thd+n @ -60dbfs = -36db, then dr = 96db. 4. total harmonic distortion + noise ratio: the ratio of the rm s sum of the noise and the distortion components to the rms value of the signal. 5. xtalk: attenuation measurement from one channel to the other one. measuremen t is performed by stimulated one channel with a 997hz / -10dbfs sinewave and le aving the other chan nel unstimulated. 6. mute attenuation: attenuation measurement of a -10dbfs / 997hz input signal when concerned gain is set to mute. thd total harmonic distortion 0dbfs input - 10k load - -88 -80 db 20mw output - 32 load - -65 -60 db 20mw output - 16 load - -60 -55 db p o output power 32 load - thd < -40db or 1% 30 mw 16 load - thd < -40db or 1% 50 mw xtalk left / right channel separation (5) 10k ac coupled load 90 db 16 dc coupled load 60 db g byp bypass gain -1 0 +1 db mute attenuation (6) 80 - - db table 10-6. analog sidetone path: microphone input to headphone output symbol parameter comments min typ max units v fs full scale output voltage (1) avdd / 3.3 v rms snr signal-to-noise ratio (2) avdd = 3.3v 92 97 - db avdd = 2.7v 89 94 - db dr dynamic range (3) avdd = 3.3v 92 97 - db avdd = 2.7v 89 94 - db thd total harmonic distortion 0dbfs input - 10k load - -88 -80 db 20mw output - 32 load - -65 -60 db 20mw output - 16 load - -60 -55 db p o output power 32 load - thd < -40db or 1% 30 mw 16 load - thd < -40db or 1% 50 mw xtalk left / right channel separation (5) 10k ac coupled load 90 db 16 dc coupled load 60 db g sidetone programmable gain range -30 - 0 db gain steps 2.5 3 3.5 db mute attenuation (6) 80 - - db table 10-5. analog bypass path: line / aux iliary input to headphone output symbol parameter comments min typ max units
25 11050a?pmaac?07-apr-10 AT73C246 11. pmu functional description 11.1 power manager state diagram figure 11-1. AT73C246 power manager functional state diagram AT73C246 is placed in powerdown state at vinsys rising following the pmu startup state diagram described in figure 11-2 on page 26 . from this powerdown state, normal cpu sup- plies startup is achieved throu gh validation of one of the powe r-on events. from this state, the pmu may be placed in standby state (e .g.: during cpu sleep periods) upon software request (standby event). pmu wake-up is achieved if one of the wakeup events is detected. the pmu returns to the powerdown state as soon as a power-off event is detected. a special hrst (hard-reset) state is provided to ensure complete stop and restart of the cpu supplies in case of a so ftware crash. moreover, die temperature and vdd {0,1,2,3} supplies are supervised and may generate a power-fail event in case of out-of-specification detection. powerdown (all supplies off) rstb = 0 hrst (all supplies off) rstb = 0 twi reset standby (selected supplies on) rstb = 0 run (all supplies on) rstb = 1 power-off or power-fail event power-on event & vin > 3.1v hrst_powerdown event hrst_run event hrst event wakeup event standby event hrst event hrst event standby-out or power-fail event
26 11050a?pmaac?07-apr-10 AT73C246 11.2 pmu startup and shutdown state diagram figure 11-2. AT73C246 start-up and shutdown state diagram the start-up of the AT73C246 follows the flow diagram of figure 11-2 and aims at placing the power manager in the powerdown state. when v insys rises above 2v: ?an internal v insys monitor starts and holds the internal pmu_rstn and audio_rstn signals to 0, thus forcing a complete reset of AT73C246. the pmu digital core supply voltage start : v insys monitor & v ddc = 1.8v. pmu_rstn = 0 audio_rstn = 0 v insys < 2.7v or v ddc _ko vin > 2v v insys > 2.7v & v ddc _ok pmu_rstn = 1 audio_rstn = 1 1 read config v backup < 1.8v rtc_rstn = 0 1 start ldo5 (backup) v backup > 1.8v rtc_rstn = 1 power down v backup > 1.8v start ldo5 (backup) v backup > 1.8v v insys < 2.7v off ldo5 (backup) 1
27 11050a?pmaac?07-apr-10 AT73C246 (v ddc = 1.8v) is started. during this pmu reset, the ?led? pin is driven to vinsys (led is off). ? when v ddc is ready and v insys > 2.7v, the internal reset signals previously mentioned are released, thus enabling the pmu digital core functions. ? before starting the ldo5 (rtc supply), v backup voltage is monitored an d if it is lower than 1.8v, the rtc function is resetted. in case of v backup > 1.8v, no reset is issued on the rtc function. ? at this step, the power manager is placed in powerdown state. 11.3 power manager conditional transitions 11.3.1 power-on events power-on events are validated if a ll these listed cond itions are true: ?v insys > 3.1v ? AT73C246 internal junction temperature tj < 110c ? pwren pin is high for more than 100ms (see table 11-1 on page 28 ). note: pwren pin, with internal 100k pull-down resistor, is active high (v backup level). it is possible to hard wire the pwren pin to v backup to always activate run state when v insys > 3.1v. conse- quently, using the so ftware power-off event (described in section 11.3.2 ) will lead to going back to the run state just after the powerdown state. 11.3.2 power-off events power-off events are validated if one of these listed conditions is true: ?v insys < 2.9v. ? pwren pin goes from low to high state and high state is held for more than 5s (see table 11-1 on page 28 ). ? software request: bit 0 (off) of register 0x00 (pmu_modes) is written to 1. 11.3.3 power-fail events power-fail events are validat ed if one of these list ed conditions is true: ? AT73C246 internal junction temperature tj > 130c ? any internal power fail detection signal coming from any cpu power supply (v dd0 , v dd1 , v dd2 , v dd3 ) goes from low to high level. note: in case of pwren pin hard wired high (v backup level), the power-fail events will lead to the powerdown state without possibility to go to the run state. the power manager will be able to reach the run state only after an hrst event. this prevents the power manager from oscillating between run and powerdown states in case of permanent failure on cpu supplies. 11.3.4 standby event standby event is validat ed if the following condition is true: ? software request: bit 1 (standby) of regi ster 0x00 (pmu_modes) is written to 1. 11.3.5 standby-out event standby-out event is validated if the following condition is true: ?v insys < 2.9v.
28 11050a?pmaac?07-apr-10 AT73C246 11.3.6 wakeup events wakeup events are validated if o ne of the listed condition is true: ? wakeup0 pin goes from low to high stat e and wakeup0 bit is set to ?1? (see table 11-1 ) in register 0x01 (pmu_wakeup_events). ? wakeup1 pin goes from low to high stat e and wakeup1 bit is set to ?1? (see table 11-1 ) in register 0x01 (pmu_wakeup_events). ? wakeup2 pin goes from low to high stat e and wakeup2 bit is set to ?1? (see table 11-1 ) in register 0x01 (pmu_wakeup_events). ? wakeup3 pin goes from low to high stat e and wakeup3 bit is set to ?1? (see table 11-1 ) in register 0x01 (pmu_wakeup_events). ? pwren pin goes from low to high state and high state is held for more than 10ms (see table 11-1 ) and pwren bit is set to ?1? in register 0x01 (pmu_wakeup_events). ? an rtc alarm occurs and rtc bit is set to ?1? in register 0x01 (pmu_wakeup_events). notes: 1. wakeup0 and pwren pins must be driven with v backup level, wakeup{1,2, 3} pins must be driven with v pad level. 2. if any wakeup event is triggered while AT73C246 is going from run to standby state, standby state is then first reached before wakeup event is taken into account. 11.3.7 hrst event hrst event is validated if the following condition is true: ? hrst pin goes from low to high state and high state is held for more than 1s (see table 11- 1 ). 11.3.8 hrst run events hrst run events are validated if a ll these listed cond itions are true: ? hrst pin is at low level for more than 10ms (see table 11-1 ). ?v insys > 3.1v ? AT73C246 internal junction temperature tj < 110c note: in case of 110c < tj < 130c, hrst state is maintained. the self cooling down of the die will lead to tj < 110c, thus exit of hrst state. 11.3.9 hrst powerdown events hrst powerdown events are validated if a ll of these listed c onditions are true: ? hrst pin is at low leve l for more than 10ms. ?v insys < 3.1v or AT73C246 internal junction temperature tj >130c table 11-1. events timing table pin parameter comments min typ max units pwren pin at v backup level. debouncing time. pin used as power-on event 95 100 105 ms pwren pin at v backup level. debouncing time. pin used as power-off event 4.75 5 5.25 sec pwren pin at v backup level. debouncing time. pin used as wakeup event 9.5 10 10.5 ms hrst pin at v backup level. debouncing time. pin used as hrst event 0.95 1 1.05 sec hrst pin at gnd level. debouncing time. pin used as hrst run event 9.5 10 10.5 ms pin used as hrst powerdown event
29 11050a?pmaac?07-apr-10 AT73C246 11.4 power manager state description AT73C246 ics are available with 2 factory prog rammed power sequences. the following timing diagrams refer to ?sequence a? and ?sequence b? programmed ics as defined in section 17. ?ordering information? on page 154 . see also the structure of register ?version (0x7f)?. 11.4.1 powerdown state when AT73C246 is in powerdown state: ? only v backup supply is active. vdd {0,1,2,3,4} power supplies are off. ? audio function is off. ? adc function is off. ? rstb pin is held low. ? led pin is set as input with internal 120k pull-up resistor to vinsys. ? twi registers are reset to default value. when the powerdown state is reached from the run state, the cpu power supplies are switched off sequentially as described in figure 11-3 on page 30 . wakeup0 pin pulsed to v backup level. pulse width. pin used as wakeup event 5 - - ns wakeup1 pin pulsed to v pad level. pulse width. pin used as wakeup event 5 - - ns wakeup2 pin pulsed to v pad level. pulse width. pin used as wakeup event 5 - - ns wakeup3 pin pulsed to v pad level. pulse width. pin used as wakeup event 5 - - ns table 11-1. events timing table pin parameter comments min typ max units
30 11050a?pmaac?07-apr-10 AT73C246 figure 11-3. AT73C246 - run to powerdown stat e supplies shutdown timing diagram. note: 1. vddx activity during run state is set by bit7 of register vddx_ctrl. table 11-2. run to powerdown state timing table symbol parameter comments min typ max units t pwrdown powerdown event detection time 58 62 66 s t off_audio audio codec shutdown time audio codec is off or power fail occurs 58 62 66 s audio codec is on 486 512 538 ms t off_vddx vddx shutdown time vddx is off in run state (1) 58 62 66 s vddx is on in run state (1) 4.8 5.2 5.4 ms run state supplies shutdown poweroff event powerdown state t pwrdown t off_audio t off_vdd3 v dd3 (3.3v) v dd1 (1.2v) v dd2 (1v) 3.3v 1.2v 1v rstb v dd0 (1.85v) t off_vdd1 t off_vdd0 t off_vdd2 v dd4 (codec) t off_vdd4 1.85v run state supplies shutdown poweroff event powerdown state t pwrdown t off_audio t off_vdd2 v dd2 (1v) v dd1 (1.2v) v dd3 (3.3v) 1v 1.2v 3.3v rstb v dd0 (1.85v) t off_vdd1 t off_vdd0 t off_vdd3 v dd4 (codec) t off_vdd4 1.85v sequence a sequence b
31 11050a?pmaac?07-apr-10 AT73C246 when the powerdown state is reached from the standby state, the cpu power supplies are switched off sequentially as described in figure 11-4 . figure 11-4. AT73C246 - standby to powerdown st ate supplies shutdown timing diagram. notes: 1. vddx activity during standby stat e is set by register pmu_standby_supplies. 2. vdd4 activity during run state is set by bit7 of register vdd4_ctrl. 11.4.2 run state when AT73C246 is in run state: ?vdd {0,1,2,3,5} power supplies are on. ? rstb pin is released. ? pmu functions are under software contro l (ldo4, audio codec, adc controller) ? led pin is driven according to register pmu_led (0x0b). table 11-3. standby to powerdown state timing table symbol parameter comments min typ max units t stby_out standby out event detection time 95 100 105 s t off_vddx vddx shutdown time vddx is off during standby state (1) 58 62 66 s vddx is on during standby state (1) 4.8 5.2 5.4 ms t off_vdd4 vdd4 shutdown time vdd4 is off in run state (2) 58 62 66 s vdd4 is on in run state (2) 4.8 5.2 5.4 ms standby state supplies shutdown standby_out event powerdown state t stby_out t off_vdd2 v dd2 (1v) v dd0 (1.85v) v dd3 (3.3v) 1v 1.2v rstb v dd1 (1.2v) t off_vdd1 1.85v t off_vdd0 3.3v t off_vdd3 v dd4 (codec) t off_vdd4 standby state supplies shutdown standby_out event powerdown state t stby_out t off_vdd3 v dd3 (3.3v) v dd0 (1.85v) v dd2 (1v) 3.3v 1.2v rstb v dd1 (1.2v) t off_vdd1 1.85v t off_vdd0 1v t off_vdd2 v dd4 (codec) t off_vdd4 sequence a sequence b
32 11050a?pmaac?07-apr-10 AT73C246 when run state is reached from the powerdown state, the power supplies are sequentially started-up according to the figure 11-5 figure 11-5. AT73C246 - powerdown to run state s upplies start-up timing diagram.. table 11-4. powerdown to run state timing table symbol parameter comments min typ max units t on_sys power-on event detection time 1.7 1.8 1.9 ms t on_vdd0 vdd0 start-up time 5 5.3 5.6 ms t on_vdd1 vdd1 start-up time 5 5.3 5.6 ms t on_vdd2 vdd2 start-up time 5.2 5.5 5.8 ms t on_vdd3 vdd3 start-up time 5.2 5.5 5.8 ms t reset all regulators on to rstb high 30.4 32 33.6 ms powerdown state supplies start up t on_sys run state vdd3 (3.3v) t on_vdd3 vdd0 (1.85v) t on_vdd0 vdd1 (1.2v) t on_vdd1 vdd2 (1v) 3.3v 1.85v 1.2v 1v t on_vdd2 rstb vpad level t reset pwren event sequence a sequence b powerdown state supplies start up t on_sys run state vdd2 (1v) t on_vdd2 vdd0 (1.85v) t on_vdd0 vdd1 (1.2v) t on_vdd1 vdd3 (3.3v) 1v 1.85v 1.2v 3.3v t on_vdd3 rstb vpad level t reset pwren event
33 11050a?pmaac?07-apr-10 AT73C246 when run state is reached from the stand by state, the power supplies are sequentially started-up according to the figure 11-6 . figure 11-6. AT73C246 - standby to run state s upplies start-up timing diagram. note: 1. vddx activity during standby state is set by register pmu_standby_supplies. 11.4.3 standby state when AT73C246 is in standby state: ?v backup is on. ?vdd {0,1,2,3} are on or off according to the status in register 0x03 (pmu_standby_supplies) ?vdd 4 is on or off according to the st atus in register 0x0a (vdd4_ctrl) ? audio function is off ? adc function is on or off according to the status in register 0x30 (adc_ctrl) ? rstb pin is forced to ground. ? twi pins are ignored to prevent twi registers from corruption ? led pin is driven according to register pmu_led (0x0b) to reach the standby state, the appropriate power supplies are shut down as described in the figure 11-7 on page 34 . table 11-5. standby to run state timing table symbol parameter comments min typ max units t on_sys start-up time time from validated wakeup event (end of debounce time when applicable) to vdd2 or vdd3 power on. 810 900 990 s t pfm pfm/pwm switching time time from validated wakeup event (end of debounce time when applicable) to pfm/pwm switching if applicable. 420 470 520 s t on_vddx vddx start-up time vddx is off during standby state (1) 5.2 5.4 5.7 ms vddx is on during standby state (1) 58 62 66 s t reset all regulators on to rstb high 30.4 32 33.6 ms sequence a sequence b standby s tat e supplies start up t on_sys run state wakeup event v dd3 (3.3v) t on_vdd3 t on_vdd0 t on_vdd1 v dd2 (1v) 3.3v 1.85v 1.2v 1v t on_vdd2 rstb vpad level t reset v dd3 on or off standby s tat e supplies start up t on_sys run state wakeup event v dd2 (1v) t on_vdd2 t on_vdd0 t on_vdd1 v dd3 (3.3v) 1v 1.85v 1.2v 3.3v t on_vdd3 rstb vpad level t reset v dd3 on or off v dd0 (1.85v) v dd1 (1.2v) pfm t pfm pfm v dd0 (1.85v) v dd1 (1.2v) pfm t pfm pfm pwm v dd0 pwm v dd1 pwm v dd0 pwm v dd1
34 11050a?pmaac?07-apr-10 AT73C246 figure 11-7. AT73C246 - run to standby state supplies shutdown timing diagram. note: 1. vddx activity during standby state is set by register pmu_standby_supplies. 2. vddx activity during run state is set by bit7 of register vddx_ctrl. 11.4.4 hrst state hrst state is a transition stat e used to restart the cpu: ?vdd {0,1,2,3,4} are switched off according to figure figure 11-8 on page 35 depending on the previous state ?vdd 5 is on ? rstb pin is forced to ground table 11-6. run to standby state timing table symbol parameter comments min typ max units t standby standby event detection time 150 160 170 s t pwm pfm/pwm switching time time from validated wakeu p event (end of debounce time when applicable) to pfm/pwm switching if applicable. 460 500 540 s t wait wakeup event detection window if a wakeup event occurs in this window the pmu automatically restart at the end of the standby process. 150 160 170 s t off_audio audio codec shutdown time audio codec is on 486 512 538 ms audio codec is off 58 62 66 s t off_vddx vddx shutdown time vddx is off during both stanby (1) and run (2) states. 58 62 66 s vddx is off during stanby state (1) . vddx is on during run state (2) . 4.8 5.2 5.4 ms t on_vddx vddx startup time vddx is on during stanby state (1) . vddx is off during run state (2) . 4.8 5.2 5.4 ms vddx is on during both stanby (1) and run (2) states. 58 62 66 s run state supplies shutdown standby event standby state t standby t off_audio t off_vdd2 t wait + v dd2 (1v) v dd3 (3.3v) 1v 1.2v 1.85v 3.3v rstb t off_vdd1 t off_vdd0 t off_vdd3 1.85v ( v dd3 on or off ) sequence a sequence b run s tat e supplies shutdown standby event standby state t standby t off_audio t off_vdd3 t wait + v dd3 (3.3v) v dd2 (1v) 3.3v 1.2v 1.85v 1v rstb t off_vdd1 t off_vdd0 t off_vdd2 1.85v ( v dd3 on or off ) v dd1 (1.2v) v dd0 (1.85v) t pwm pwm pwm v dd1 (1.2v) v dd0 (1.85v) t pwm pwm pwm pfm v dd0 pfm v dd1 pfm v dd0 pfm v dd1
35 11050a?pmaac?07-apr-10 AT73C246 figure 11-8. AT73C246 - hrst state supplies shutdown timing diagram. note: 1. vddx activity during run state is set by bit7 of register vddx_ctrl notes: 1. vddx activity during standby stat e is set by register pmu_standby_supplies. 2. vdd4 activity during run state is set by bit7 of register vdd4_ctrl. table 11-7. hrst state timing table from run state symbol parameter comments min typ max units t hrst hrst event detection time 58 62 66 s t off_audio audio codec shutdown time audio codec is on 486 512 538 ms audio codec is off 58 62 66 s t off_vddx vddx shutdown time vddx is off in run state (1) 58 62 66 s vddx is on in run state (1) 4.8 5.2 5.4 ms t off_pmu pmu functions shutdown time 1.4 1.5 1.6 ms table 11-8. hrst state timing table from standby state symbol parameter comments min typ max units t hrst hrst event detection time 58 62 66 s t off_audio audio codec shutdown time audio codec is on 486 512 538 ms audio codec is off 58 62 66 s t off_vddx vddx shutdown time vddx is off during standby state (1) 58 62 66 s vddx is on during standby state (1) 4.8 5.2 5.4 ms t off_vdd4 vdd4 shutdown time vdd4 is off in run state (2) 58 62 66 s vdd4 is on in run state (2) 4.8 5.2 5.4 ms t off_pmu pmu functions shutdown time 1.4 1.5 1.6 ms run / standby / powerdown s tat e supplies shutdown hrst_event event hrst state t hrst t off_vdd3 t off_audio v dd3 (3.3v) v dd1 (1.2v) v dd2 (1v) 3.3v 1.2v 1.85v 1v rstb v dd0 (1.85v) t off_vdd1 t off_vdd0 t off_vdd2 pmu functions (ldo4, adc, led,...) t off_pmu run / standby / powerdown state supplies shutdown hrst_event event hrst state t hrst t off_vdd2 t off_audio v dd2 (1v) v dd1 (1.2v) v dd3 (3.3v) 1v 1.2v 1.85v 3.3v rstb v dd0 (1.85v) t off_vdd1 t off_vdd0 t off_vdd3 pmu functions (ldo4, adc, led,...) t off_pmu sequence a sequence b
36 11050a?pmaac?07-apr-10 AT73C246 11.5 dcdc0 and dcdc1 functional description dcdc0 and dcdc1 are 2 identical high performa nce synchronous step-down (buck) convert- ers. they feature: ? 2 control modes: pfm and pwm, ? a soft start circuit, ? a software programmable output voltage betw een 0.8 and 3.6v with automatic ramping for dvs application, ? an over-current-protection circuit, ? a 180 degree out of phase operating mode. 11.5.1 pfm and pwm control modes pulse frequency modulation control is an hysteretic c ontrol of the output vo ltage. it is specially intended for light loads (< 50ma typ). in this mode, the dcdc converter exhibits a very low qui- escent current (< 50 a) thus achieving very high efficiency at light loads. the frequency of operation in this mode is not fixed but proportional to the load current. pulse width modulation control is a fixed frequency, variable dut y cycle control of the dcdc converter. it has a fast and precise feedback loop specially intended to handle hard loads and low output ripple voltage. at start-up, dcdc0 and dcdc1 operate in pwm mode. this way, high load at cpu boot are properly handled. through software control in registers vdd0_ctrl (0x06) and vdd1_ctrl (0x07), the user may enter the low-power mo de (pfm) when the application consumption is reduced. 11.5.2 soft-start circuit dcdc0 and dcdc1 feature a soft start circuit to prevent high input current while charging the output capacitor from 0v to the default output voltage. typically, the in-rush current at start-up (with no load) is limited to 30 ma. 11.5.3 output voltage programming dcdc0 and dcdc1 output voltages can be managed through so ftware control in registers vdd0_ctrl (0x06) and vdd1_ctrl (0x07). 50mv steps are provided from 0.8v to 3.6v. it is recommended to use the automatic ramping function in register pmu_supply_ctrl (0x04) to achieve smooth operation. when the dvs_vdd {0,1} bit is active (default mode), output voltages are ramped from the current value to the final value in 50mv / 280us steps. for users who intend to disable the dvs_vdd {0,1} bit, a maximum of 4 steps (= 200mv) per 100us is allowed. at power up, dcdc0 and dcdc1 default output vo ltages are respectively 1.85v and 1.20v. for different default output voltages, please contact atmel. 11.5.4 180 out-of-phase operation dcdc0 and dcdc1 can be oper ated in-phase or at 180 out-of-phase accord ing to the selec- tion bit in register pmu_supply_ctrl (0x04) . when operated in phase both converters will start charging their inductor at the same time. when operated at 180 out-of-phase, the inductor charge start time will be shifted by half a 2mhz clock delay (= 250ns) from one converter to the other. this latter sc heme tends to average the input current of both dcdc converters.
37 11050a?pmaac?07-apr-10 AT73C246 11.6 ldo2 functional description ldo2 is a linear voltage regulator intended to supply cpu core voltages in the range 0.8v to 1.35v. its maximum input voltage is 3.6v. thus, it must not be wired to the vin plane with vin- sys, vin0, vin1, vin3 and vin4 if vin is above 3.6v. consider ing its low-outp ut voltage and for the sake of efficiency and power dissipation, the user may connect it at the output of dcdc0. this ldo features: ? a soft start circuit, ? a software programmable output voltage betw een 0.8 and 1.35v with automatic ramping for dvs application. 11.6.1 soft-start circuit ldo2 features a soft start circui t to prevent high input current while charging the output capaci- tor from 0v to the default output voltage. this soft start ci rcuit limits the input current during 5ms (+/-5%) at startup to 200ma in typical conditi ons. after this delay, ldo2 recovers full current capability. 11.6.2 output voltage programming ldo2 output voltage can be managed through so ftware control in register vdd2_ctrl (0x08). 50mv steps are provided from 0.8v to 1.35v. it is recommended to use the automatic ramping function in register pmu_supply_ctrl (0x 04) to achieve smooth operation. when the dvs_vdd2 bit is active (default mode), output voltages are ramped from the current value to the final value in 50mv / 600us steps. at power up, ldo2 default output voltage is 1v. for different default output voltage, please con- tact atmel. 11.7 ldo3 and ldo4 functional description ldo3 and ldo4 are low dropout linear voltage regulators intended to supply cpu peripherals (i/os, analog functions) in the range 2.7v to 3.6v. they can be operated directly from a 5.5v maximum input voltage. they feature: ? a soft start circuit, ? a software programmable output between 2.7v and 3.6v voltage with automatic ramping for dvs application, 11.7.1 soft-start circuit ldo3 and ldo4 feature a soft start circuit to pr event high input current while charging the out- put capacitor from 0v to the def ault output voltage. this soft star t circuit limits the input current during 5ms (+/-5%) at startup to 200ma in typical conditions. af ter this delay, ldo3(4) recovers full current capability. 11.7.2 output voltage programming ldo3 and ldo4 output voltages can be managed through software control in registers vdd3_ctrl (0x09) and vdd4_ctrl (0x0a). 50mv st eps are provided from 2.7v to 3.6v. it is recommended to use the automatic ramping function in register pmu_supply_ctrl (0x04) to achieve smooth operation. when the dvs_vdd {3,4} bit is active (default mode), output voltages are ramped from the current value to the final value in 50mv / 600us steps.
38 11050a?pmaac?07-apr-10 AT73C246 at power up, ldo3 an ldo4 default output volt ages are both 3.3v. for different default output voltages, please contact atmel. 11.8 power fail detectors AT73C246 features a power fail detector on each cpu supplies (v dd0 , v dd1 , v dd2 , v dd3 ). this function is made of a comparat or that toggles each time on e the listed power supplies goes below a defined threshold. the comparator toggling is considered by the pmu digital state machine as a power-fail event. the threshold value of the power fail detector is pr oportional to the output voltage of the regula- tor. it is not a fixed voltage, it is adapt ed to the programmed output voltage. the default threshold value is set according to register pmu_rst_lvl (0x05) and can be programmed to another value through twi access. for other defaul t threshold values at startup, please contact atmel. 11.9 measurement bridge and 10-bit adc AT73C246 features a 10-channel measurement chain including: ? a multiplexer + attenuator fo llowed by a unity gain buffer ? a 300ks/s 10-bit sar adc. adc function is enabled through the register adc_ctrl (0 x30). adc_mux_1 (0x31) and adc_mux_2 (0x32) allow the selection of inputs to be measured. 1 to 10 inputs can be selected. the adc will then perf orm serial conversion on these inputs and write th e correspond- ing result in registers 0x33 to 0x49. 2 sampling modes are provided to perform periodic conversions: ? max speed ? low speed. to enter these modes, refer to the sampling period bits (ts) in the register adc_ctrl (0x30). when max_speed mode is select ed, the adc runs at 300ks/s and loop without any dead time over the selected inputs. when a low_speed sa mpling period is select ed, the adc performs a set of input conversions (1 to 10) at 300ks/s and then wait for one sampling period (defined by ts bits) to start another set of conversions.
39 11050a?pmaac?07-apr-10 AT73C246 figure 11-9. measurement bridge and 10-bit adc block diagram. v refp adc v insys v dd0 v dd1 v dd2 v dd3 v dd4 ana0 ana1 ana2 ana3 adc_ana0_msb adc_ana0_lsb adc_ana_lsb 0 0 0 twi registers adcout <9:0> v refn v ddc v refp gndsys buffer 0x30 adc_ctrl 0x31 adc_mux_1 0x32 adc_mux_2 mux 10 1 10-channel resistive attenuator
40 11050a?pmaac?07-apr-10 AT73C246 11.10 real time clock (rtc) user interface figure 11-10. rtc block diagram note: 1. values in the version register vary wit h the version of the ip block implementation. rtc addr rtc data 3 rtc data 2 rtc data 1 rtc data 0 control regi s ter s tat u s clear command regi s ter mode regi s ter time regi s ter calendar regi s ter time alarm regi s ter calendar alarm regi s ter s tat u s regi s ter interrupt enable regi s ter interrupt di s able regi s ter interrupt ma s k regi s ter valid entry regi s ter ver s ion regi s ter re s erved regi s ter rtc ctrl rtc_ s el rtc_en rtc_write rtc table 11-9. register mapping offset register name access reset 0x00 control register rtc_cr read-write 0x0 0x04 mode register rtc_mr read-write 0x0 0x08 time register rtc_timr read-write 0x0 0x0c calendar register rtc_calr read-write 0x01819819 0x10 time alarm register rtc_timalr read-write 0x0 0x14 calendar alarm register rtc_calalr read-write 0x01010000 0x18 status register rtc_sr read-only 0x0 0x1c status clear command register rtc_sccr write-only --- 0x20 interrupt enable register rtc_ier write-only --- 0x24 interrupt disable register rtc_idr write-only --- 0x28 interrupt mask register rtc_imr read-only 0x0 0x2c valid entry register rtc_ver read-only 0x0 0xfc version register (1) rtc_version read-only --- 0xfc reserved register --- --- ---
41 11050a?pmaac?07-apr-10 AT73C246 11.10.1 rtc register read/write operation figure 11-11. rtc read operation figure 11-12. rtc write operation rtc_en rtc_ s el rtc_write rtc_data rtc_addr write rtc_addr read rtc_data 3 read rtc_data2 read rtc_data1 read rtc_data0 write 02 @rtc_ctrl write 0 3 @rtc_ctrl write 02 @rtc_ctrl write 00 @rtc_ctrl rtc_en = 0 rtc_ s el = 1 rtc_write = 0 rtc_en = 1 rtc_ s el = 1 rtc_write = 0 rtc_en = 0 rtc_ s el = 1 rtc_write = 0 rtc_en = 0 rtc_ s el = 0 rtc_write = 0 twi acce ss rtc_en rtc_ s el rtc_write rtc_data rtc_addr write rtc_addr write rtc_data 3 write rtc_data2 write rtc_data1 write rtc_data0 write 06 @rtc_ctrl write 07 @rtc_ctrl write 06 @rtc_ctrl write 00 @rtc_ctrl rtc_en = 0 rtc_ s el = 1 rtc_write = 1 rtc_en = 1 rtc_ s el = 1 rtc_write = 1 rtc_en = 0 rtc_ s el = 1 rtc_write = 1 rtc_en = 0 rtc_ s el = 0 rtc_write = 0 twi acce ss
42 11050a?pmaac?07-apr-10 AT73C246 11.10.2 rtc control register name: rtc_cr access: read-write address: 0x00 ? updtim: update request time register 0 = no effect. 1 = stops the rtc time counting. time counting consists of second, minute and hour counters. time counters can be programmed once this bit is set and acknowledged by the bit ackupd of the status register. ? updcal: update request calendar register 0 = no effect. 1 = stops the rtc calendar counting. calendar counting consists of day, date, month, year and century count ers. calendar counters can be programmed once this bit is set. ? timevsel: time ev ent selection the event that generates the flag ti mev in rtc_sr (status register) depends on the value of timevsel. 0 = minute change. 1 = hour change. 2 = every day at midnight. 3 = every day at noon. ? calevsel: calendar event selection the event that ge nerates the flag calev in rtc_sr depends on the value of calevsel. 0 = week change (every mo nday at time 00:00:00). 1 = month change (every 01 of each month at time 00:00:00). 2, 3 = year change (every january 1 at time 00:00:00) 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?????? cal evsel 15 14 13 12 11 10 9 8 ?????? timevsel 76543210 ??????updcalupdtim
43 11050a?pmaac?07-apr-10 AT73C246 11.10.3 rtc mode register name: rtc_mr access: read-write address: 0x04 ? hrmod: 12-/24-hour mode 0 = 24-hour mode is selected. 1 = 12-hour mode is selected. all non-significant bits read zero. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????hrmod
44 11050a?pmaac?07-apr-10 AT73C246 11.10.4 rtc time register name: rtc_timr access: read-write address: 0x08 ? sec: current second the range that can be set is 0 - 59 (bcd). the lowest four bits encode the unit s. the higher bits encode the tens. ? min: current minute the range that can be set is 0 - 59 (bcd). the lowest four bits encode the unit s. the higher bits encode the tens. ? hour: current hour the range that can be set is 1 - 12 (bcd) in 12-hour mode or 0 - 23 (bcd) in 24-hour mode. ? ampm: ante meridiem post meridiem indicator this bit is the am/pm in dicator in 12-hour mode. 0 = am. 1 = pm. all non-significant bits read zero. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?ampm hour 15 14 13 12 11 10 9 8 ?min 76543210 ?sec
45 11050a?pmaac?07-apr-10 AT73C246 11.10.5 rtc calendar register name: rtc_calr access: read-write address: 0x0c ?cent: current century the range that can be set is 19 - 20 (bcd). the lowest four bits encode the unit s. the higher bits encode the tens. ? year: current year the range that can be set is 00 - 99 (bcd). the lowest four bits encode the unit s. the higher bits encode the tens. ? month: current month the range that can be set is 01 - 12 (bcd). the lowest four bits encode the unit s. the higher bits encode the tens. ? day: current day the range that can be set is 1 - 7 (bcd). the coding of the number (which number represents which day) is us er-defined as it has no effect on the date counter. ? date: current date the range that can be set is 01 - 31 (bcd). the lowest four bits encode the unit s. the higher bits encode the tens. all non-significant bits read zero. 31 30 29 28 27 26 25 24 ?? date 23 22 21 20 19 18 17 16 day month 15 14 13 12 11 10 9 8 year 76543210 ?cent
46 11050a?pmaac?07-apr-10 AT73C246 11.10.6 rtc time alarm register name: rtc_timalr access: read-write address: 0x10 ? sec: second alarm this field is the alarm field corresponding to the bcd-coded second counter. ? secen: second alarm enable 0 = the second-matching alarm is disabled. 1 = the second-matching alarm is enabled. ? min: minute alarm this field is the alarm field corresponding to the bcd-coded minute counter. ? minen: minute alarm enable 0 = the minute-matching alarm is disabled. 1 = the minute-matching alarm is enabled. ? hour: hour alarm this field is the alarm field corresponding to the bcd-coded hour counter. ? ampm: am/pm indicator this field is the alarm field corresponding to the bcd-coded hour counter. ? houren: hour alarm enable 0 = the hour-matching alarm is disabled. 1 = the hour-matching alarm is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 houren ampm hour 15 14 13 12 11 10 9 8 minen min 76543210 secen sec
47 11050a?pmaac?07-apr-10 AT73C246 11.10.7 rtc calendar alarm register name: rtc_calalr access: read-write address: 0x14 ? month: month alarm this field is the alarm field corresponding to the bcd-coded month counter. ? mthen: month alarm enable 0 = the month-matching alarm is disabled. 1 = the month-matching alarm is enabled. ? date: date alarm this field is the alarm field corresponding to the bcd-coded date counter. ? dateen: date alarm enable 0 = the date-matching alarm is disabled. 1 = the date-matching alarm is enabled. 31 30 29 28 27 26 25 24 dateen ? date 23 22 21 20 19 18 17 16 mthen ? ? month 15 14 13 12 11 10 9 8 ???????? 76543210 ????????
48 11050a?pmaac?07-apr-10 AT73C246 11.10.8 rtc status register name: rtc_sr access: read-only address: 0x18 ? ackupd: acknowledge for update 0 = time and calendar registers cannot be updated. 1 = time and calendar registers can be updated. ? alarm: alarm flag 0 = no alarm matching condition occurred. 1 = an alarm matching condition has occurred. ? sec: second event 0 = no second event has occurred since the last clear. 1 = at least one second event has occurred since the last clear. ? timev: time event 0 = no time event has occurred since the last clear. 1 = at least one time event has occurred since the last clear. the time event is selected in the timevsel field in rtc_ctrl (control register) and can be any one of the following events: minute change, hour chan ge, noon, midnight (day change). ? calev: calendar event 0 = no calendar event has occurred since the last clear. 1 = at least one calendar event has occurred since the last clear. the calendar event is selected in the calevsel field in rtc_cr and can be any one of the following events: week change, month change and year change. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? calev timev sec alarm ackupd
49 11050a?pmaac?07-apr-10 AT73C246 11.10.9 rtc status clear command register name: rtc_sccr access: write-only address: 0x1c ? ackclr: acknowledge clear 0 = no effect. 1 = clears corresponding status flag in the status register (rtc_sr). ? alrclr: alarm clear 0 = no effect. 1 = clears corresponding status flag in the status register (rtc_sr). ? secclr: second clear 0 = no effect. 1 = clears corresponding status flag in the status register (rtc_sr). ? timclr: time clear 0 = no effect. 1 = clears corresponding status flag in the status register (rtc_sr). ? calclr: calendar clear 0 = no effect. 1 = clears corresponding status flag in the status register (rtc_sr). 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? calclr timclr secclr alrclr ackclr
50 11050a?pmaac?07-apr-10 AT73C246 11.10.10 rtc interrupt enable register name: rtc_ier access: write-only address: 0x20 ? acken: acknowledge update interrupt enable 0 = no effect. 1 = the acknowledge for update interrupt is enabled. ? alren: alarm interrupt enable 0 = no effect. 1 = the alarm interrupt is enabled. ? secen: second event interrupt enable 0 = no effect. 1 = the second periodic interrupt is enabled. ? timen: time event interrupt enable 0 = no effect. 1 = the selected time event interrupt is enabled. ? calen: calendar event interrupt enable 0 = no effect. ? 1 = the selected calendar event interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? calen timen secen alren acken
51 11050a?pmaac?07-apr-10 AT73C246 11.10.11 rtc interrupt disable register name: rtc_idr access: write-only address: 0x24 ? ackdis: acknowledge update interrupt disable 0 = no effect. 1 = the acknowledge for update interrupt is disabled. ? alrdis: alarm interrupt disable 0 = no effect. 1 = the alarm interrupt is disabled. ? secdis: second event interrupt disable 0 = no effect. 1 = the second periodic interrupt is disabled. ? timdis: time event interrupt disable 0 = no effect. 1 = the selected time event interrupt is disabled. ? caldis: calendar ev ent interrupt disable 0 = no effect. 1 = the selected calendar event interrupt is disabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? caldis timdis secdis alrdis ackdis
52 11050a?pmaac?07-apr-10 AT73C246 11.10.12 rtc interrupt mask register name: rtc_imr access: read-only address: 0x28 ? ack: acknowledge update interrupt mask 0 = the acknowledge for update interrupt is disabled. 1 = the acknowledge for update interrupt is enabled. ? alr: alarm interrupt mask 0 = the alarm interrupt is disabled. 1 = the alarm interrupt is enabled. ? sec: second event interrupt mask 0 = the second periodic interrupt is disabled. 1 = the second periodic interrupt is enabled. ? tim: time event interrupt mask 0 = the selected time event interrupt is disabled. 1 = the selected time event interrupt is enabled. ? cal: calendar event interrupt mask 0 = the selected calendar event interrupt is disabled. 1 = the selected calendar event interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? cal tim sec alr ack
53 11050a?pmaac?07-apr-10 AT73C246 11.10.13 rtc valid entry register name: rtc_ver access: read-only address: 0x2c ? nvtim: non-valid time 0 = no invalid data has been detected in rtc_timr (time register). 1 = rtc_timr has contained invalid data since it was last programmed. ? nvcal: non-valid calendar 0 = no invalid data has been detected in rtc_calr (calendar register). 1 = rtc_calr has contained invalid data since it was last programmed. ? nvtimalr: non-valid time alarm 0 = no invalid data has been detected in rtc_timalr (time alarm register). 1 = rtc_timalr has contained invali d data since it was last programmed. ? nvcalalr: non-valid calendar alarm 0 = no invalid data has been detected in rtc_calalr (calendar alarm register). 1 = rtc_calalr has contained invalid data since it was last programmed. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????nvcalalrnvtimalrnvcalnvtim
54 11050a?pmaac?07-apr-10 AT73C246 11.10.14 rtc version register name: rtc_version access: read-only address: 0xfc ? version reserved. value subject to change. no funcionality associat ed. this is the atmel intern al version of the macrocell. ?mfn reserved. value subject to change. no funcionality associated. 11.11 die temperature sensor the AT73C246 features a die temper ature sensor for prot ection reasons. if the junction temper- ature rises above the shutdown threshold for a minimum time of 1ms (+/- 5%), the power manager event t j > 130c is asserted. in a similar fashion, if the temperature falls through the restart threshold for more than 1ms, the power manager event t j <110c is asserted. the two internal thresholds shutdown and restart are defined in section 9.11 ?die temperature sensor? on page 21 . 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????? mfn 15 14 13 12 11 10 9 8 ???? version 76543210 version
55 11050a?pmaac?07-apr-10 AT73C246 12. audio codec fun ctional description 12.1 description AT73C246 features a high quality, low power stereo audio codec with integrated headphone amplifier. the playback channel accommodates 16 to 24-b it stereo programmable format entering the dig- ital audio interface (i 2 s) and delivers an internal analog audio output through a 100db snr sigma delta stereo dac. an ou tput mixer allows to mix this dac output with a line / aux or microphone input. a 16-32 ohms stereo headphone amplifier with virtual ground output provides a 97db snr out- put for line / headphone loads. the virtual ground output allows to remove 2 space demanding coupling capacitors on board. on the record side, a multiplexer can select between a main stereo line input and a stereo auxil- iary input such as an fm radio. a stereo microphone input with up to 46db gain is provided. a stereo input mixer allows mixi ng between line (or aux) and microphone channels before entering a 96db snr stereo sigma delta adc. the digital audio signal is then digitally filtered and trans- ferred to the i 2 s audio interface. 12.2 audio codec block diagram figure 12-1. audio codec block diagram mux adc dac dsp + audio controller bypass 0 -> -30db -77/+6db v mid -34 -> +12db 0 -> +46db linl auxl micl micln micbias avdd 200k vmid agnd hpd et codec bias mclk bclk lrfs dai pa o i2s hpvcm hpl mux adc dac bypass 0 -> -30db -77/+6db -34 -> +12db linr auxr hpr 200k 2k 1db step 1db step 1db step 1db step 1db step 1db step 1db step 0 -> +46db micr micrn 1db step
56 11050a?pmaac?07-apr-10 AT73C246 12.3 audio codec controls figure 12-2. audio codec controls bclkinv enasr stdby enac linboth rinboth daimode mclksel selfs rhsboth lhsboth i2s interface master sscmode wl asrtime pathsel audio controller adcl dacl adcr digital processor dacr gsdt sidetone -30 to +0db linesel onlinr onadcr onadcl ondacl ondacr monodac monoadc -35 to +12db gain control 1db step 3db step + + deemp deemp 0 to +46db 1db step onmicr micrvol inrvol mixliner + onmixr mixmicr -35 to 12db 1db step 0 to +46db 1db step onlinl onmicl gain control inlvol miclvol linesel mixmicl + onmixl mixlinel onplayback onplayback hpl hpr hpvcm mutemicl muteinl micldiff micrdiff equalizer mutedacl swapdac swapadc equalizer mutedacr mutehpl -77 to 6db 1db step mutehpr hprvol dcblock onhpr hpdet onhpl/r gsdt sidetone -30 to +0db onsidetone onbypass onsidetone onbypass 3db step fx3d fx3d -77 to 6db 1db step muteinr micl micln lineinl auxinl micr micrn lineinr auxinr mutemicr dcblock onhpl onmicbias micdetlev vmid avdd micbias agnd twi dcblock vmid hplvol 2k 200k 200k onmicbias
57 11050a?pmaac?07-apr-10 AT73C246 12.4 audio controller the audio controller sequences the power-up and power-down of the audio codec sub-functions (mic.amp / adc / dac / ?). during these transitioning phases, the controller also manages the gain steps to fade them in and out, thus providing smooth operation. depending on the application, two modes are provided: 1. automatic path control dedicated to the major audio path scenarios (those described in table 13-25 on page 95 ), this mode enables the whole audio path setup only via "pathsel" bits in register autostart (0x10). 2. custom path control dedicated to audio path scenarios not described in the previously mentioned table, this mode brings the flexibility to start manually the audio sub-functions. the following figure shows the global context of the audio codec control. figure 12-3. audio codec typical control sequence apply supply & mclk configure analog & digital interfaces 2 unmute codec 3 start audio codec in standby 4 software wait 5 custom path control 6 automatic path control shutdown audio codec 8 unset dcblock bit 9 remove mclk & supply 10 1 7 registers to set : - audio_control (0x11) (set dcblock bit here) - mic_control (0x12) - dai_control (0x13) - frame_control (0x14) register to set : - mute (0x15) register to set : - autostart (0x10) typically 350ms. - see vmid section. registers to set - see dedicated sections. register to set : - autostart (0x10) software wait at least 1s. - see ?power-off time? section. register to set : - audio_control (0x11) - see ?ac/dc coupled load management? section.
58 11050a?pmaac?07-apr-10 AT73C246 12.4.1 audio codec general recommendations 12.4.1.1 v mid ?v mid is the common mode voltage of the audio codec analog core. it is recommended to decouple this voltage with a 1uf capacitor to ensure low noise operation as well as slow (thus silent) transients at codec power up and power down. ?the v mid capacitor is charged and discharged when ever the enac bit is set or cleared. particularly, placing the audio codec in standby mode does not discharge the v mid capacitor. the software wait operations in the previous diagram (step #5 and step #8 in ?audio codec typical control sequence? on page 57 ) should accommodate v mid 's settling time constant. see ?audio codec bias? on page 22. . 12.4.1.2 ac / dc coupled load management ? by default the audio codec is in dc-coupled load configuration: dcb lock = 0 in register audio_control(0x11). in this case, a virtual ground voltage is provided on pin hpvcm (a buffered version of v mid ). it allows to directly connect headphones or line loads between hpvcm and hpl(or r) without any coupling capacitors. to prevent any audio pop at start-up or shutdown in this dc coupling mode, the audio codec fastly starts hpl, hpr and hpvcm outputs shorted all together. no software management is required to achieve pop-less operation. ? if output loads are ac coupled to the headphone amplifier, the audio codec dcblock bit must be set and unset as described in ?audio codec typical control sequence? on page 57 . this bit partially controls the two switches s1 and s2 described in the following figure. when dcblock = 1 and the headphone amplifier is off, the output coupling capacitors are charged and discharged by the amplifier ?vmid_ buffer?. in order to achieve silent startup and shutdown, the following rules must be respected: ? dcblock = 0 at supply power-on and po wer-off. this ensures that the ldo4 power-on and power-off transients are not transmitted to the audio loads. ? dcblock = 1 when enac = 1. particularly, dcblock must be set before enac=1 and unset after enac=0. this en sures that the full vmid waveform is properly buffered to the output loads. ? dcblock = 1 after enac = 0 and until v mid capacitor is fully discharged. at codec shutdown (enac=0), vmid will discharge slowly. the vmid_buffer ensures slow and silent discharge of the output coupling capacitors, and needs s1 and s2 to be closed.
59 11050a?pmaac?07-apr-10 AT73C246 figure 12-4. ac / dc coupled load management schematic view figure 12-5. audio codec typical startup and shutdown waveforms with ac coupled loads. 12.4.1.3 mute register by default, the audio codec starts muted. to enable the audio processing, the mute register (0x15) must be cleared. unmute operation can be performed before or after releasing the standby mode. during operation, this register provides a convenient way of muting the audio signal without changing the various gain registers. 12.4.1.4 master clock input (mclk) the audio controller is clocked by mclk pin. therefore a clock must be present at this pin before each codec control change. particularly, the master clock must be present at power-on, power-off, gain change, path change. the master clock must also be available when fully analog path are used. 12.4.1.5 power-off conditions three audio codec power-off conditions can occur: ? sofware request (enac = 0 in autostart regist er). in this case, the codec is smoothly powered off by the audio controller. ? pmu power-off event or standby event (as defined in section 11.3 ?power manager conditional transitions? on page 27 ). in this case, the codec is smoothly powered off with a at 7 3 c246 vmid agnd avdd vdd4 vin4 ldo4 200k 10uf 200k enac 1uf hpl hpr dcblock.onhp left right vmid buffer s 1 s 2 c l c r r r r l vdd4 vmid hp(l/r) dcblock enac standby s1 & s2 s1 and s2 opened by audio codec
60 11050a?pmaac?07-apr-10 AT73C246 500ms timeout. contrary to the first point, wh ich has no timeout, the audio power-off time limit is here fixed to 500ms. beyond this limi t, the codec is hardly re seted as in the following point. ? pmu power-fail event. in this case, the pmu finite state machine makes an immediate hard reset of the audio codec to ensure fast shutdow n. this case may generate an audible click / pop noise. 12.4.1.6 power-off time at power-off, the audio controller needs to perform several controls on audio codec sub-func- tions and to discharge the output coupling capacitors. therefore, the codec?s power-off time is divided into: ? a digital power-off time and, ? an analogue one. during this power-off phase, the codec?s master clock and suppl y must be present. see ?audio codec power-off waveforms? on page 60. figure 12-6. audio codec power-off waveforms the digital power-off time depends on the number of controls (power-off, gain steps ramping, ...) to perform and for this reason strongly varies according to: ? the master clock frequency, ? the current path, ? the current gains and ? the current automatic soft ramping time (asr_time in audi o_control(0x11)). in worst case conditions (slo west clock, maximum asr_time, maximum complexity audio path, maximum gains everywhere), the power-off time reaches 3 seconds. duri ng this period, the vdd4 vmid audio signal enac digital power-o time analog power-o time mclk
61 11050a?pmaac?07-apr-10 AT73C246 master clock must be running to properly shutdo wn the codec. this time linearly varies with asr_time value. see table 12-1 the analog power-off time corresponds to the vmid?s discharge time specified in ?audio codec bias? on page 22 : t mid_off . finally, the wait step #8 in ?audio codec typical control sequence? on page 57 needs to acco- modate the digital power-off time + the analog power-off time. 12.4.2 automatic path configuration in this automatic path mode, the audio path co ntrol is fully managed by the autostart(0x10) register and more precisely by the following bits: ? enac (enable audio codec), ? standby (1) (audio standby) and ? pathsel (audio path selection). when the audio controller detects a change in thes e bits, it generates sequential controls to the audio codec sub-functions (power-up, gain ramp ing, unmute,?) with the right timing and order. notes: 1. audio standby does not refer to the pmu standby state as defined in ?AT73C246 power manager functional state diagram? on page 25 . the audio standby mode activated by reg- ister autostart (0x10) only refers to the audio codec controller. 12.4.2.1 standby release once the codec is started and in standby mode (enac=1 and standby=1, step #5 in ?audio codec typical control sequence? on page 57 ), the audio path is simp ly selected by pathsel bits. at standby release (standby=0), the audio controller will: ? power-up the requested audio sub-functions. to do so, the audio controller makes write accesses to the registers ? input_control (0x1e), ? output_control (0x1f) and ? input_mixer (0x20). ? ramp-up the concerned path gains from mute to their current register value. notes: 1. changing pathsel value with standby=1 does not changes the codec state. it remains in standby mode. 2. the audio controller always ensures minimum power consumption by powering only needed sub-functions. 3. audio parameters (volume, mute, effects?) can be modified before or after releasing the standby mode. table 12-1. audio codec maximum power-off time asr_time power-off time (ms) 00 375 01 750 10 1500 11 3000
62 11050a?pmaac?07-apr-10 AT73C246 12.4.2.2 pause management with standby bit to pause the audio codec activity and reduce power consumption to few hundreds of micro- amps, the standby bit can be activated in re gister autostart (0x1 0). the audio codec will then: ? softly ramp down all the path concerned gains down-to mute and ? power off all the audio sub-functions. the registers input_control (0x1e), output_control (0x1f), and input_mixer (0x20) are modified by the audio controller. notes: 1. placing the codec in standby mode maintain s the common mode voltage at vmid pin and thus allows to re-start fastly, 2. standby release is simply achieved by clearing the standby bit (standby = 0). the proce- dure described in ?standby release? on page 61 applies. 12.4.2.3 on-the-fly path change the audio controller is able to softly switch fr om one audio path configuration to another without shutting down the codec nor entering the standb y mode. as soon as it detects a change in the pathsel value, the following mechanism occurs: ? power up and/or power down of the audio sub-f unctions according to the final state to reach. this operation generates automatic changes in the registers input_control (0x1e), output_control (0x1f), and input_mixer (0x20). ? ramp up and/or ramp down of the concerned path gain. notes: 1. a channel may be temporarily and smoothly switched off and on to reach the new path. 2. any software write operation in the regist ers input_control (0x1e), output_control (0x1f), and input_mixer (0x20) will generate a series of control on the audio codec sub- functions. in automatic path control, the order of the write operations in those registers is of prime importance. please note that changing th ose registers updates the used audio path without updating the pathsel valu e. therefore, thes e write operations ar e not recommended and must be limited to simple ones (for example changing linesel bit in register input_control (0x1e) ). 12.4.2.4 audio codec shutdown the audio controller will star t to shutdown the codec if en ac = 0. the shutdown sequence is made of the following steps: ? softly ramp down all the path concerned gains down-to mute, ? power off all the audio sub-functions and, ? power off the common voltage vmid. notes: 1. in this mode, the power consumption is reduced to few hundreds of na. 2. the common mode voltage power-off follows vmid time constant and thus may take a few hundreds of milliseconds depending on vmid capacitor. see ?audio codec bias? on page 22. a software example of audio codec control using aut omatic path control is provided in the sec- tion ?basic audio codec setting using automatic path control? on page 134 . 12.4.3 custom path configuration in this custom path mode, the audio path control is managed by the following registers: ? autostart (0x10) (enac and standby bits only) ? audio_control (0x11) (enconf and custconf bits only)
63 11050a?pmaac?07-apr-10 AT73C246 ? input_control (0x1e) ? output_control (0x1f) ? input_mixer (0x20) like in the automatic path c onfiguration, the audio controll er will sequence audio codec sub- functions on/off as well as gain stepping. howeve r, the audio path is no more selected via the "pathsel" value in re gister autostart. to specify a custom audio path: ? the bit custconf in register audio_control (0x11) must be set to '1' to specify the 'custom' path configuration mode. ? the registers input_control (0x1e), ou tput_control (0x1f), and input_mixer (0x20) are set to define the audio path, ? the bit enconf in register audio_control (0x11) is pulsed to '1' to enable the audio controller sequencing. notes: 1. ?pulsed to ?1? ?means written to ?1? and then written to ?0?. 2. in this mode, the standby bit behaves like in the automatic mode. it is possible to place the codec in standby mode to reduce power consum ption during audio pause by simply setting the standby bit to 1. standby release is achieved by clearing this bit. 3. on-the-fly path change is achieved by mo difying the registers input_control (0x1e), output_control (0x1f) , and input_mixer (0x20) to define the new audio path config- uration and then pulsing to '1' the enconf bit. in this case, a channel may be temporarily (and smoothly) switched off and on to reach the new configuration. 4. changing the three registers input_control (0x1e), output_control (0x1f) , and input_mixer (0x20) with the enconf bit set to ?1? makes the changes to take effect imme- diately. therefore, the order of write operations is of prime importance. it is then recommended to write these registers with enconf set to 0 and then pulse enconf to ?1? once the new audio path is fully specified. knowing the final state to reach, the audio controller is able to sequence the controls with the right order and timings to ensure noise-free operation. 5. in this custom mode, the audio controller ma y forbid any configuration that does not make sense. for example, it will prev ent the headphone amplifier from being switched on if it has no input source (dac, microphone, or line). 6. it is possible and sometimes convenient to switch from an automatically set path to a custom one. in this case, the audio controller softly per forms the required path change. however, acti- vating an automatic path configur ation from a current custom path configuration is not allowed. the audio codec must be switched off first (enac=0). a software example of audio codec control using custom path control is provided in the section ?basic audio codec setting using custom path control? on page 135 . 12.5 audio codec power consumpti on versus programmed audio path unless otherwise specified: ?a vdd = 3.3v ? mclk = 12.288mhz , fs = 48khz ? all gains set to 0db ? no audio signal ?t a = 25c. ? headphone amplifier set in ac coupling mode.
64 11050a?pmaac?07-apr-10 AT73C246 ? current consumptions don?t account for load consumption and are measured in a vdd pin and v insys pin. table 12-2. audio path power consumption path_sel audio path description consumption units v insys a vdd 00000 no path 0.10 0.61 ma 00001 dac playback digital in - headphone out 1.80 5.2 ma 00010 mic sidetone microphone in - headphone out 0.10 2.65 ma 00011 aux bypass aux in - headphone out 0.10 2.65 ma 00100 line bypass line in - headphone out 0.10 2.65 ma 00101 mic record mic in - digital out 2.00 3.40 ma 00110 aux record aux in - digital out 2.00 3.40 ma 00111 line record line in - digital out 2.00 3.40 ma 01000 mic sidetone + record mic in - headphone and digital out 2.00 5.05 ma 01001 aux bypass + record aux in - headphone and digital out 2.00 5.05 ma 01010 line bypass + record line in - headphone and digital out 2.00 5.05 ma 01011 mic + aux record mic + aux in - digital out 2.00 3.70 ma 01100 mic + line record mic + line in - digital out 2.00 3.70 ma 01101 dac playback + mic sidetone digital + mic in - headphone out 1.80 5.60 ma 01110 dac playback + aux bypass digital + aux in - headphone out 1.80 5.60 ma 01111 dac playback + line bypass digital + line in - headphone out 1.80 5.60 ma 10000 dac playback + mic sidetone + aux bypass digital + mic + aux in - headphone out 1.80 5.85 ma 10001 dac playback + mic sidetone + line bypass digital + mic + line in - headphone out 1.80 5.85 ma 10010 dac playback and mic record digital in - headphone out mic in - digital out 3.80 8.00 ma 10011 dac playback and aux record digital in - headphone out aux in - digital out 3.80 8.00 ma 10100 dac playback and line record digital in - headphone out line in - digital out 3.80 8.00 ma 10101 dac playback + mic sidetone and mic record digital + mic in - headphone out mic in - digital out 3.80 8.00 ma 10110 dac playback + aux bypass and aux record digital + aux in - headphone out aux in - digital out 3.80 8.00 ma
65 11050a?pmaac?07-apr-10 AT73C246 10111 dac playback + line bypass and line record digital + line in - headphone out line in - digital out 3.80 8.00 ma 11000 dac playback + mic sidetone + aux bypass and mic + aux record digital + mic + aux in - headphone out mic + aux in - digital out 3.80 8.25 ma 11001 dac playback + mic sidetone + line bypass and mic + line record digital + mic + line in - headphone out mic + line in - digital out 3.80 8.25 ma table 12-2. audio path power consumption path_sel audio path description consumption units v insys a vdd
66 11050a?pmaac?07-apr-10 AT73C246 12.6 digital audio interface 12.6.1 general description AT73C246 features a 16 to 24-bit multi-mode master / slave i 2 s port. the following modes are provided: ?i2s, ? left justified, ? right justified, and ? ssc the i 2 s port is configured through register i2s_control (0x13) and frame_control (0x14). for each of the listed modes, the data transfer is described in the following sections. the following table provides authorized mclk / fs ratios and associated filter types: note: 1. 12.0000 mhz case is not provided if dai is configured in right-justified and master mode in dai_control (0x13) and frame_control registers (0x14). 12.6.2 data transfer: i2s mode figure 12-7. n-bit i2s mode (fs = 44.1khz - mclk = 256 x fs) table 12-3. authorized mclk / fs ratios & filter types 12 mhz (1) 12.288 mhz 18.432 mhz 11.2896 mhz 16.9344 mhz 8 khz 0 2 2 na na 16 khz 0 2 2 na na 32 khz 0 2 2 na na 48 khz 3 1 1 na na 96 khz 4 3 3 na na 22.05 khz 1 na na 1 1 44.1 khz 1 na na 1 1 88.2 khz 3 na na 3 3 r 0 r 1 r 2 r 3 r n-1 r n l 0 l n-1 l n n bits right channel n bits left channel lrfs bclk sdout mclk sdin
67 11050a?pmaac?07-apr-10 AT73C246 12.6.3 data transfer: left justified mode figure 12-8. n-bit left justified mode (fs = 44.1khz - mclk = 256 x fs) 12.6.4 data transfer: right justified mode figure 12-9. n-bit right justified mode (fs = 44.1khz - mclk = 256 x fs) r 0 r 1 r 2 r 3 r n-1 r n l 0 l n-1 l n l n-2 r n-2 n bits right channel n bits left channel lrfs bclk sdout mclk sdin r 0 r 1 r 2 r 3 r n-1 r n l 0 l n-1 l n l n-2 r n-2 n bits right channel n bits left channel lrfs bclk sdout mclk sdin
68 11050a?pmaac?07-apr-10 AT73C246 12.6.5 timing specifications figure 12-10. timing diagram of data interface (i2s mode) 12.7 digital filters transfer function 12.7.1 dac frequency response the following diagrams are referred to fs = 1 (sampling frequency). figure 12-11. dac type 0 frequency response ls b ls b msb msb ls b lrfs bclk dai dao v xl v xh v il v ih v il v ih word n-1 right channel word n left channel word n right channel t lrclk t bclk t hsdx t lsdx t lrclk table 12-4. digital audio interfac etiming specifications parameter symbols min typ max unit left/right word cycle time t lrclk 1 / (2 x f s )s bit clock period t bclk t mclk / 2 s bclk posedge to {dai, dao and lrfs} change hold time t hsdx 5ns {dai, dao and lrfs} change to bclk posedge setup time t lsdx 5ns overall ripple
69 11050a?pmaac?07-apr-10 AT73C246 figure 12-12. dac type 1 frequency response figure 12-13. dac type 2 frequency response figure 12-14. dac type 3 frequency response overall ripple overall ripple overall ripple
70 11050a?pmaac?07-apr-10 AT73C246 figure 12-15. dac type 4 frequency response 12.7.2 adc frequency response the following diagrams are referred to fs = 1 (sampling frequency). figure 12-16. adc type 0 frequency response figure 12-17. adc type 1 frequency response overall ripple ripple overall ripple overall
71 11050a?pmaac?07-apr-10 AT73C246 figure 12-18. adc type 2 frequency response figure 12-19. adc type 3 frequency response figure 12-20. adc type 4 frequency response ripple overall ripple overall ripple overall
72 11050a?pmaac?07-apr-10 AT73C246 12.7.3 de-emphasis filter frequency response 12.7.3.1 de-emphasis filter: frequency response & error (fs = 32khz) figure 12-21. de-emphasis filter: frequency response & error (fs = 32khz) 12.7.3.2 de-emphasis filter: frequency response & error (fs = 44.1khz) figure 12-22. de-emphasis filter: frequency response & error (fs = 44.1khz) 12.7.3.3 de-emphasis filter: frequency response & error (fs = 48khz) figure 12-23. de-emphasis filter: frequency response & error (fs = 48khz) response (db) fequency (hz) response (db) fequency (hz) error response response (db) fequency (hz) response (db) fequency (hz) error response response (db) fequency (hz) response (db) fequency (hz) error response
73 11050a?pmaac?07-apr-10 AT73C246 12.7.4 equalizer frequency response the following figures show the frequency response of the equalizer function implemented in the d/a channels. figure 12-24. bass filters response figure 12-25. medium filters response fs db fs db
74 11050a?pmaac?07-apr-10 AT73C246 figure 12-26. treble filters response 12.8 analog audio interfaces 12.8.1 microphone inputs the following figures show recommended ap plication circuits for microphone inputs configurations: ? mono - single-ended and differential microphone ? stereo - single ended and differential microphone ? long-wires microphone recommended resistor / capacitor / inductor value may be tuned to the final application, depending on: ? the microphone specified load resistance, ? the high pass filter desired corner frequency, ? the level and frequency of unwanted signals to be rejected. depending also on desired high frequency filterin g: common-mode or differential, the differential suggested application diag rams may be modified. fs db
75 11050a?pmaac?07-apr-10 AT73C246 figure 12-27. mono - single ended and differential microphone applications figure 12-28. stereo - single ended and differential microphone applications figure 12-29. long wires microphone applications micbia s micl micln micr micrn avdd vdd4 vin4 ldo4 2k m 2k 1uf 10uf nc nc nc 2.2nf at 7 3 c246 10uf micbia s micl micln micr micrn avdd vdd4 vin4 ldo4 2k m 1k 1uf 10uf nc nc 2.2nf at 7 3 c246 1uf 1k 10uf micbia s micl micln micr micrn avdd vdd4 vin4 ldo4 2k m 2k 1uf 2.2nf at 7 3 c246 10uf nc m 1uf 2.2nf 2k nc nc micbia s micl micln micr micrn avdd vdd4 vin4 ldo4 2k m 1k 1uf 2.2nf at 7 3 c246 1uf 1k 10uf nc m 1uf 2.2nf 1uf 1k 1k 470 10uf 470 10uf 470 10uf 470 10uf micbia s micl micln micr micrn avdd vdd4 vin4 ldo4 2k 2k 1uf 10uf nc nc nc 2.2nf at 7 3 c246 10uf m 1nf 10uh long wires micbia s micl micln micr micrn avdd vdd4 vin4 ldo4 2k 1k 1uf 2.2nf at 7 3 c246 1uf 1k 10uf nc 1uf 2.2nf 1uf 1k 1k 10uh 10uh m 1nf 10uh 10uh m 1nf long wires long wires 470 470 10uf 10uf
76 11050a?pmaac?07-apr-10 AT73C246 12.8.2 aux / line inputs figure 12-30. aux and line input application circuits 12.8.3 line / headphone outputs figure 12-31. ac coupled output application circuits figure 12-32. dc coupled (capless) application circuits auxl auxr linl linr at 7 3 c246 3 . 3 uf 10nf 100 3 . 3 uf 10nf 100 on-board audio ic s ource (fm receiver, ...) 3 . 3 uf 10nf 100k 100 3 . 3 uf 10nf 100k 100 jack hpr hpvcm hpl at 7 3 c246 nc 3 . 3 uf 100k 3 . 3 uf 100k jack line-output 100 100 hpr hpvcm hpl at 7 3 c246 nc 33 0uf 100k 33 0uf 100k jack headphone output 16 / 3 2 ohms hpr hpvcm hpl at 7 3 c246 hpr hpvcm hpl at 7 3 c246 jack headphone output 16 / 3 2 ohms diff. in / diff. out power amp. diff. in / diff. out power amp.
77 11050a?pmaac?07-apr-10 AT73C246 13. two wire interface and control registers 13.1 two-wire interface (twi) protocol the two-wire interface interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds up to 400 kbits per second, based one a byte oriented transfer format. the twi is sl ave only and single byte access. the interface adds flexibility to the power s upply solution, enabling ldo regulators to be con- trolled depending on the instantaneous application requirements. the AT73C246 has the following 7-bit address:1001001. attempting to read data from register addresses not listed in this section results in 0xff being read out. ? twck is an input pin for the clock ? twd is an open-drain pin that dr ives or receives the serial data the data put on the twd line must be 8 bits long. data is transferred m sb first. each byte must be followed by an acknowledgement. each transfer begins with a start condition and terminates with a stop condition. ? a high-to-low transition on twd while twck is high defines a start condition. ? a low-to-high transition on twd while twck is high defines a stop condition. figure 13-1. twi start/stop cycle figure 13-2. twi data cycle after the host initiates a start condition, it se nds the 7-bit slave addres s defined above to notify the slave device. a read/write bit follows (read = 1, write = 0). the device acknowledges each received byte. the first byte sent after device address and r/w bit is the address of the device register the host wants to read or write. for a write operation the data follows the internal address twd twck start stop twd twck start address r/w ack data ack data ack stop
78 11050a?pmaac?07-apr-10 AT73C246 for a read operation a repeated start condition needs to be generated followed by a read on the device. figure 13-3. twd write operation figure 13-4. twd read operation ?s = start ?p = stop ?w = write ? r = read ? a = acknowledge ? n = not acknowledge ? addr = device address ? iaddr = internal address a iaddr a p data a s addr w twd a iaddr a s addr w s addr r a data np twd
79 11050a?pmaac?07-apr-10 AT73C246 13.2 pmu register tables 13.2.1 register mapping table 13-1. register mapping addrname 76543210 0x00 pmu_modes - - - - - standby pwrdown run 0x01 pmu_wakeup_events - - rtc pwren wakeup3 wakeup2 wakeup1 wakeup0 0x02 pmu_wakeup_trig - - rtcr pwren wakeup3 wakeup2 wakeup1 wakeup0 0x03 pmu_standby_supplies - - lp_vdd1 lp_vdd0 vdd3 vdd2 vdd1 vdd0 0x04 pmu_supply_ctrl - - in_phase dvs_vdd4 dvs_vdd3 dvs_vdd2 dvs_vdd1 dvs_vdd0 0x05 pmu_rst_level rst_vdd3 rst_vdd2 rst_vdd1 rst_vdd0 0x06 vdd0_ctrl on_vdd0 lpmode vdd0_sel 0x07 vdd1_ctrl on_vdd1 lpmode vdd1_sel 0x08 vdd2_ctrl on_vdd2 - - vdd2_sel 0x09 vdd3_ctrl on_vdd3 - - vdd3_sel 0x0a vdd4_ctrl on_vdd4 - - vdd4_sel 0x0b pmu_led ton_led period_led blink on_led 0x0c pmu_mask - - - - - - rtc_alarm rtc_it 0x0d pmu_it - - - - - - rtc_alarm rtc_it 0x0e pmu_wakeup_supplies - - - - vdd0_wup vdd1_wup vdd2_wup vdd3_wup 0x10 autostart - enac standby path_sel 0x11 audio_control - bclkinv dcblo ck enconf custconf enasr asr_time 0x12 mic_control - - micldiff mi crdiff micdet onmicbias micdet_st 0x13 dai_control - - master mclksel 0x14 frame_control sscmode wl daimode selfs 0x15 mute mutedacl mutedacr muteinl muteinr mutemicl mutemicr mutehpl mutehpr 0x16 miclvol - - miclvol 0x17 micrvol - - micrvol 0x18 inlvol inlboth inlvol 0x19 inrvol inrboth inrvol 0x1a hplvol hplvol 0x1b hprvol hprvol 0x1c hp_control hpdet_st lhpboth rhpboth 0x1d audio_effects 3dfx_depth on3dfx swap_dac swap_adc mono_dac mono_adc ondeemp 0x1e input_control - linesel onmic l onmicr onadcl onadcr onlinl onlinr 0x1f output_control - onsidetone onplayback onbypass onhpl onhpr ondacl ondacr 0x20 input_mixer - - mixmicl mixmicr mixlinel mixliner onmixl onmixr 0x21 sidetone_vol - - - sidetone_vol 0x22 equalizer - - - - eq_sel 0x30 adc_ctrl on_adc on_buf ts 0x31 adc_mux_1 - vin - vdd4 vdd3 vdd2 vdd1 vdd0 0x32 adc_mux_2 - - - - ana3 ana2 ana1 ana0 0x33 adc_ana0_msb adc<9:2>
80 11050a?pmaac?07-apr-10 AT73C246 0x34 adc_ana0_lsb - - - - - - adc<1:0> 0x35 adc_ana1_msb adc<9:2> 0x36 adc_ana1_lsb - - - - - - adc<1:0> 0x37 adc_ana2_msb adc<9:2> 0x38 adc_ana2_lsb - - - - - - adc<1:0> 0x39 adc_ana3_msb adc<9:2> 0x3a adc_ana3_lsb - - - - - - adc<1:0> 0x3b adc_vdd0_msb adc<9:2> 0x3c adc_vdd0_lsb - - - - - - adc<1:0> 0x3d adc_vdd1_msb adc<9:2> 0x3e adc_vdd1_lsb - - - - - - adc<1:0> 0x3f adc_vdd2_msb adc<9:2> 0x40 adc_vdd2_lsb - - - - - - adc<1:0> 0x41 adc_vdd3_msb adc<9:2> 0x42 adc_vdd3_lsb - - - - - - adc<1:0> 0x43 adc_vdd4_msb adc<9:2> 0x44 adc_vdd4_lsb - - - - - - adc<1:0> 0x47 adc_vin_msb adc<9:2> 0x48 adc_vin_lsb - - - - - - adc<1:0> 0x49 adc_ana_lsb adc_ana3<1:0> adc_ana2<1:0> adc_ana1<1:0> adc_ana0<1:0> 0x50 rtc_ctrl - - - - - rtc_write rtc_sel rtc_en 0x51 rtc_addr rtc_addr 0x52 rtc_data0 rtc_data0 0x53 rtc_data1 rtc_data1 0x54 rtc_data2 rtc_data2 0x55 rtc_data3 rtc_data3 0x56 backup_ctrl - - - - osc_updt osc_en osc_stat rst_bkup 0x7f version software_tag version table 13-1. register mapping addrname 76543210
81 11050a?pmaac?07-apr-10 AT73C246 13.2.2 pmu control name : pmu_modes access : read / write address : 0x00 notes: 1. please refer to section 11. ?pmu functional description? on page 25 2. ?run? bit is read-only. only ?standby ? and ?pwrdown? bits can be written 76543210 -----standbypwrdownrun table 13-2. pmu_modes (0x00) structure bit name description reset value 7:3 - unused 00000 2 standby standby request 0: default value. 1: standby request. reset to 0 at standby exit. 0 1pwrdown powerdown request 0: default value. 1: powerdown request. reset to 0 when powerdown state reached. 0 0 run run mode 0
82 11050a?pmaac?07-apr-10 AT73C246 name : pmu_wakeup_events access : read / write address : 0x01 note: please refer to section 11. ?pmu functional description? on page 25 76543210 - - rtc pwren wakeup3 wakeup2 wakeup1 wakeup0 table 13-3. pmu_wakeup_events (0x01) structure bit name description reset value 7:6 - unused 00 5rtc wake up by rtc alarm input 0: disabled 1: enabled 0 4pwren wake up by pwren input 0: disabled 1: enabled 0 3 wakeup3 wake up by wakeup3 input 0: disabled 1: enabled 0 2 wakeup2 wake up by wakeup2 input 0: disabled 1: enabled 0 1 wakeup1 wake up by wakeup1 input 0: disabled 1: enabled 0 0 wakeup0 wake up by wakeup0 input 0: disabled 1: enabled 1
83 11050a?pmaac?07-apr-10 AT73C246 name : pmu_wakeup_trig access : read only address : 0x02 note: please refer to section 11. ?pmu functional description? on page 25 76543210 - - rtcr pwren wakeup3 wakeup2 wakeup1 wakeup0 table 13-4. pmu_wakeup_trig (0x02) structure bit name description reset value 7:6 - unused 00 5 rtcr wakeup_event trigged on rtc alarm 0 4 pwren wakeup_event trigged on pwren 0 3 wakeup3 wakeup_event trigged on wakeup3 0 2 wakeup2 wakeup_event trigged on wakeup2 0 1 wakeup1 wakeup_event trigged on wakeup1 0 0 wakeup0 wakeup_event trigged on wakeup0 0
84 11050a?pmaac?07-apr-10 AT73C246 name : pmu_standby_supplies access : read / write address : 0x03 76543210 - - lp_vdd1 lp_vdd0 vdd3 vdd2 vdd1 vdd0 table 13-5. pmu_standby_supplies (0x03) structure bit name description reset value 7:6 - unused 00 5 lp_vdd1 vdd1 low power mode in standby 0: full power (pwm) 1: low power (pfm) 1 4 lp_vdd0 vdd0 low power mode in standby 0: full power (pwm) 1: low power (pfm) 1 3 vdd3 vdd3 in standy state 0: off 1: on 1 2 vdd2 vdd2 in standy state 0: off 1: on 0 1 vdd1 vdd1 in standy state 0: off 1: on 0 0 vdd0 vdd0 in standy state 0: off 1: on 1
85 11050a?pmaac?07-apr-10 AT73C246 name : pmu_supply_ctrl access : read / write address : 0x04 76543210 - - in_phase dvs_vdd4 dvs_vdd3 dvs_vdd2 dvs_vdd1 dvs_vdd0 table 13-6. pmu_supply_ctrl (0 x04) structure bit name description reset value 7:6 - unused 00 5 in_phase dcdc0 and dcdc1 phase operation 0: out-of phase 1: in-phase 0 4 dvs_vdd4 dvs function on vdd4 0: off 1: on 1 3 dvs_vdd3 dvs function on vdd3 0: off 1: on 1 2 dvs_vdd2 dvs function on vdd2 0: off 1: on 1 1 dvs_vdd1 dvs function on vdd1 0: off 1: on 1 0 dvs_vdd0 dvs function on vdd0 0: off 1: on 1
86 11050a?pmaac?07-apr-10 AT73C246 name : pmu_rst_lvl access : read / write address : 0x05 76543210 rst_vdd3 rst_vdd2 rst_vdd1 rst_vdd0 table 13-7. pmu_rst_lvl (0x05) structure bit name description reset value 7:6 rst_vdd3 rst level on vdd3 01 5:4 rst_vdd2 rst level on vdd2 10 3:2 rst_vdd1 rst level on vdd1 10 1:0 rst_vdd0 rst level on vdd0 11 table 13-8. vddx reset level selection table rst_vddx rst level 00 0.85 x vddx 01 0.90 x vddx 10 0.92 x vddx 11 0.95 x vddx
87 11050a?pmaac?07-apr-10 AT73C246 name : vdd0_ctrl access : read / write address : 0x06 76543210 on_vdd0 lpmode vdd0_sel table 13-9. vdd0_ctrl (0x06) structure bit name description reset value 7 on_vdd0 vdd0 on/off 0: off 1: on 0 6lpmode vdd0 low power mode 0: full power (pwm) 1: low power (pfm) 0 5:0 vdd0_sel vdd0 voltage selection 010101 table 13-10. vdd0 voltage selection table vdd0_sel vdd0 (v) vdd0_sel v dd0 (v) vdd0_sel vdd0 (v) 000000 0.80 010011 1.75 100110 2.70 000001 0.85 010100 1.80 100111 2.75 000010 0.90 010101 1.85 101000 2.80 000011 0.95 010110 1.90 101001 2.85 000100 1.00 010111 1.95 101010 2.90 000101 1.05 011000 2.00 101011 2.95 000110 1.10 011001 2.05 101100 3.00 000111 1.15 011010 2.10 101101 3.05 001000 1.20 011011 2.15 101110 3.10 001001 1.25 011100 2.20 101111 3.15 001010 1.30 011101 2.25 110000 3.20 001011 1.35 011110 2.30 110001 3.25 001100 1.40 011111 2.35 110010 3.30 001101 1.45 100000 2.40 110011 3.35 001110 1.50 100001 2.45 110100 3.40 001111 1.55 100010 2.50 110101 3.45 010000 1.60 100011 2.55 110110 3.50 010001 1.65 100100 2.60 110111 3.55 010010 1.70 100101 2.65 111000 3.60
88 11050a?pmaac?07-apr-10 AT73C246 name : vdd1_ctrl access : read / write address : 0x07 76543210 on_vdd1 lpmode vdd1_sel table 13-11. vdd1_ctrl (0x07) structure bit name description reset value 7 on_vdd1 vdd1 on / off 0: off 1: on 0 6lpmode vdd1 low power mode 0: full power (pwm) 1: low power (pfm) 0 5:0 vdd1_sel vdd1 voltage selection 001000 table 13-12. vdd1 voltage selection table vdd1_sel vdd1 (v) vdd1_sel v dd1 (v) vdd1_sel vdd1 (v) 000000 0.80 010011 1.75 100110 2.70 000001 0.85 010100 1.80 100111 2.75 000010 0.90 010101 1.85 101000 2.80 000011 0.95 010110 1.90 101001 2.85 000100 1.00 010111 1.95 101010 2.90 000101 1.05 011000 2.00 101011 2.95 000110 1.10 011001 2.05 101100 3.00 000111 1.15 011010 2.10 101101 3.05 001000 1.20 011011 2.15 101110 3.10 001001 1.25 011100 2.20 101111 3.15 001010 1.30 011101 2.25 110000 3.20 001011 1.35 011110 2.30 110001 3.25 001100 1.40 011111 2.35 110010 3.30 001101 1.45 100000 2.40 110011 3.35 001110 1.50 100001 2.45 110100 3.40 001111 1.55 100010 2.50 110101 3.45 010000 1.60 100011 2.55 110110 3.50 010001 1.65 100100 2.60 110111 3.55 010010 1.70 100101 2.65 111000 3.60
89 11050a?pmaac?07-apr-10 AT73C246 name : vdd2_ctrl access : read / write address : 0x08 76543210 on_vdd2 - - vdd2_sel table 13-13. vdd2_ctrl (0x08) structure bit name description reset value 7 on_vdd2 vdd2 on / off 0: off 1: on 0 6:5 - unused 00 4:0 vdd2_sel vdd2 voltage selection 00100 table 13-14. vdd2 voltage selection table vdd2_sel vdd2 (v) 00000 0.80 00001 0.85 00010 0.90 00011 0.95 00100 1.00 00101 1.05 00110 1.10 00111 1.15 01000 1.20 01001 1.25 01010 1.30 01011 1.35
90 11050a?pmaac?07-apr-10 AT73C246 name : vdd3_ctrl access : read / write address : 0x09 76543210 on_vdd3 - - vdd3_sel table 13-15. vdd3_ctrl (0x09) structure bit name description reset value 7 on_vdd3 vdd3 on / off 0: off 1: on 0 6:5 - unused 00 4:0 vdd3_sel vdd3 voltage selection 01100 table 13-16. vdd3 voltage selection table vdd3_sel vdd3 (v) 00000 2.70 00001 2.75 00010 2.80 00011 2.85 00100 2.90 00101 2.95 00110 3.00 00111 3.05 01000 3.10 01001 3.15 01010 3.20 01011 3.25 01100 3.30 01101 3.35 01110 3.40 01111 3.45 10000 3.50 10001 3.55 10010 3.60
91 11050a?pmaac?07-apr-10 AT73C246 name : vdd4_ctrl access : read / write address : 0x0a 76543210 on_vdd4 - - vdd4_sel table 13-17. vdd4_ctrl (0x0a) structure bit name description reset value 7 on_vdd4 vdd4 on / off 0: off 1: on 0 6:5 - unused 00 4:0 vdd4_sel vdd4 voltage selection 01100 table 13-18. vdd4 voltage selection table vdd4_sel vdd4 (v) 00000 2.70 00001 2.75 00010 2.80 00011 2.85 00100 2.90 00101 2.95 00110 3.00 00111 3.05 01000 3.10 01001 3.15 01010 3.20 01011 3.25 01100 3.30 01101 3.35 01110 3.40 01111 3.45 10000 3.50 10001 3.55 10010 3.60
92 11050a?pmaac?07-apr-10 AT73C246 name : pmu_led access : read / write address : 0x0b note: in case of ton_led = 175ms, period_led=5s and blink=1 selection, the led pin is driven according to the following diagram. during 9 clock periods (internal rc 32khz oscillator) the pin is driven to 0, and during 1 clock period the pin is configured as ?input? with an internal pull up resis- tor to vinsys. figure 13-5. led pin timing diagram for ton _led = 175ms and period_led=5s 76543210 ton_led period_led blink on_led table 13-19. pmu_led (0x0b) structure bit name description reset value 7:5 ton_led led ?on? time 000 4:2 period_led led blinking period 010 1blink blinking function on / off 0: off 1: on 0 0 on_led led on / off 0: off 1: on 0 table 13-20. led blinking function parameters selection table ton_led led ?on? time (ms) period_led blinking period (s) 000 25 000 0.5 001 50 001 1 010 75 010 2 011 100 011 3 100 125 100 4 101 150 101 5 110 175 110 6 111 200 111 8 internal r c 32khz led pin 9 x 32khz clock periods pin forced to ?0?
93 11050a?pmaac?07-apr-10 AT73C246 name : pmu_mask access : read / write address : 0x0c name : pmu_it access : read only address : 0x0d 76543210 ------ rtc_ala rm rtc_it table 13-21. pmu_mask (0x0c) structure bit name description reset value 7:2 - unused 111111 1rtc_alarm mask rtc alarm 0: not masked 1: masked 1 0rtc_it mask rtc interrupt 0: not masked 1: masked 1 76543210 ------ rtc_ala rm rtc_it table 13-22. pmu_it (0x0d) structure bit name description reset value 7:2 - unused 000000 1rtc_alarm rtc alarm interrupt 0: default value 1: rtc alarm has occurred. reset to 0 at read. 0 0rtc_it rtc interrupt 0: default value 1: rtc interrupt has occurred. reset to 0 at read. 0
94 11050a?pmaac?07-apr-10 AT73C246 name : pmu_wakeup_supplies access : read / write address : 0x0e 76543210 ----vdd0_wupvdd1_wupvdd2_wupvdd3_wup table 13-23. pmu_wakeup_supplies (0x0e) structure bit name description reset value 7:4 - unused 0000 3 vdd0_wup vdd0 value at wakeup 0: programmed value 1: default value 1 2 vdd1_wup vdd1value at wakeup 0: programmed value 1: default value 1 1 vdd2_wup vdd2 value at wakeup 0: programmed value 1: default value 1 0 vdd3_wup vdd3 value at wakeup 0: programmed value 1: default value 1
95 11050a?pmaac?07-apr-10 AT73C246 name : autostart access : read / write address : 0x10 76543210 - enac standby path_sel table 13-24. autostart (0x10) structure bit name description reset value 7 - unused 0 6enac audio codec on / off 0: off 1: on 0 5 standby audio standby mode on / off 0: audio codec active 1: audio codec in standby 1 4:0 path_sel audio path selection 00000 table 13-25. audio path selection table path_sel audio path 00000 no path 00001 dac playback digital in - headphone out 00010 mic sidetone microphone in - headphone out 00011 aux bypass aux in - headphone out 00100 line bypass line in - headphone out 00101 mic record mic in - digital out 00110 aux record aux in - digital out 00111 line record line in - digital out 01000 mic sidetone + record mic in - headphone and digital out 01001 aux bypass + record aux in - headphone and digital out 01010 line bypass + record line in - headphone and digital out 01011 mic + aux record mic + aux in - digital out 01100 mic + line record mic + line in - digital out 01101 dac playback + mic sidetone digital + mic in - headphone out 01110 dac playback + aux bypass digital + aux in - headphone out 01111 dac playback + line bypass digital + line in - headphone out 10000 dac playback + mic sidetone + aux bypass digital + mic + aux in - headphone out 10001 dac playback + mic sidetone + line bypass digital + mic + line in - headphone out 10010 dac playback and mic record digital in - headphone out mic in - digital out
96 11050a?pmaac?07-apr-10 AT73C246 10011 dac playback and aux record digital in - headphone out aux in - digital out 10100 dac playback and line record digital in - headphone out line in - digital out 10101 dac playback + mic sidetone and mic record digital + mic in - headphone out mic in - digital out 10110 dac playback + aux bypass and aux record digital + aux in - headphone out aux in - digital out 10111 dac playback + line bypass and line record digital + line in - headphone out line in - digital out 11000 dac playback + mic sidetone + aux bypass and mic + aux record digital + mic + aux in - headphone out mic + aux in - digital out 11001 dac playback + mic sidetone + line bypass and mic + line record digital + mic + line in - headphone out mic + line in - digital out table 13-25. audio path selection table path_sel audio path
97 11050a?pmaac?07-apr-10 AT73C246 name : audio_control access : read / write address : 0x11 76543210 - bclkinv dcblock enconf cust_co nf enasr asr_time table 13-26. audio_control (0x11) structure bit name description reset value 7- - 0 6blckinv bit clock inversion on i 2 s port 0: not inverted 1: inverted 0 5 dcblock headphone output coupling configuration 0: dc coupled (capless operation) 1: ac coupled 0 4 enconf custom configuration enable 0: default value. 1: custom configuration is send to audio controller. 0 3 cust_conf custom audio configuration 0: audio path are set with path_sel 1: custom audio path set by software 0 2 enasr gain soft ramping on / off 0: off 1: on 1 1:0 asr_time gain soft ramping timing selection 11 table 13-27. gain soft ramping ti ming selection table asr_time timing 00 mclk / (32 x 512) 01 mclk / (64 x 512) 10 mclk / (128 x 512) 11 mclk / (256 x 512)
98 11050a?pmaac?07-apr-10 AT73C246 name : mic_control access : read / write address : 0x12 76543210 - - micldiff micrdiff micdet onmicbias micdet_st table 13-28. mic_control (0x1 2) structure bit name description reset value 7:6 - unused 00 5micldiff left microphone differential configuration 0: single-ended 1: differential 0 4 micrdiff right microphone differential configuration 0: single-ended 1: differential 0 3:2 micdet microphone detector threshold 00 1 onmicbias microphone bias generator on / off 0: off 1: on 0 0micdet_st micbias pin microphone detector status bit 0: no microphone detected 1: microphone detected 0 table 13-29. microphone detector threshold selection table micdet micbias pin level (v) 00 avdd - 0.1 01 avdd - 0.2 10 avdd - 0.3 11 avdd - 0.4
99 11050a?pmaac?07-apr-10 AT73C246 name : dai_control access : read / write address : 0x13 note: 1. the master mode is not provided for 12. 0000 mhz clock case and right-justified mode on dai. 76543210 ----master mcl ksel table 13-30. dai_control (0x13) structure bit name description reset value 7:4 - unused 0000 3 master (1) master / slave operation on dai port 0: slave 1: master 0 2:0 mclksel audio master clock frequency selection 001 table 13-31. audio master clock selection table mclksel mclk (mhz) mclksel mclk (mhz) 000 12.000 100 16.9344 001 12.288 101 - 010 11.2896 110 - 011 18.432 111 -
100 11050a?pmaac?07-apr-10 AT73C246 name : frame_control access : read / write address : 0x14 note: 1. the right-justified mode is not provided fo r 12.0000 mhz clock case and master mode on dai. 76543210 sscmode wl dai_mode selfs table 13-32. frame_control (0x14) structure bit name description reset value 7 sscmode ssc mode for dai 0: dai according to dai_mode bits 1: ssc mode 0 6:5 wl word length selection 11 4:3 dai_mode digital audio interface mode control 00 2:0 selfs audio frame frequency selection 011 table 13-33. digital audio interface word length selection table wl mode 00 16 01 18 10 20 11 24 table 13-34. digital audio interface mode selection table daimode mode 00 i2s 01 left-justified 10 right-justified (1) 11 n/a table 13-35. audio sampling frequency selection table selfs fs (khz) selfs fs (khz) 000 8 100 96 001 16 101 22.050 010 32 110 44.100 011 48 111 88.200
101 11050a?pmaac?07-apr-10 AT73C246 name : mute access : read / write address : 0x15 76543210 mutedacl mutedac r muteinl muteinr mutemicl mutemicr mutehpl mutehpr table 13-36. mute (0x15) structure bit name description reset value 7 mutedacl dac left mute 0: active 1: muted 1 6 mutedacr dacr right mute 0: active 1: muted 1 5 muteinl aux / line left mute 0: active 1: muted 1 4 muteinr aux / line right mute 0: active 1: muted 1 3mutemicl mic left mute 0: active 1: muted 1 2mutemicr mic right mute 0: active 1: muted 1 1 mutehpl headphone left mute 0: active 1: muted 1 0 mutehpr headphone right mute 0: active 1: muted 1
102 11050a?pmaac?07-apr-10 AT73C246 name : miclvol access : read / write address : 0x16 76543210 -- miclvol table 13-37. miclvol (0x16) structure bit name description reset value 7:6 - unused 00 5:0 miclvol microphone left volume selection 000000 table 13-38. microphone left volume selection table miclvol gain(db) miclvol gain(db) miclvol gain(db) 000000 0 010000 16 100000 32 000001 1 010001 17 100001 33 000010 2 010010 18 100010 34 000011 3 010011 19 100011 35 000100 4 010100 20 100100 36 000101 5 010101 21 100101 37 000110 6 010110 22 100110 38 000111 7 010111 23 100111 39 001000 8 011000 24 101000 40 001001 9 011001 25 101001 41 001010 10 011010 26 101010 42 001011 11 011011 27 101011 43 001100 12 011100 28 101100 44 001101 13 011101 29 101101 45 001110 14 011110 30 101110 46 001111 15 011111 31 other values 46
103 11050a?pmaac?07-apr-10 AT73C246 name : micrvol access : read / write address : 0x17 76543210 -- micrvol table 13-39. micrvol (0x17) structure bit name description reset value 7:6 - unused 0 5:0 micrvol microphone right volume selection 000000 table 13-40. microphone right volu me selection table micrvol gain(db) micrvol gain(db) micrvol gain(db) 000000 0 010000 16 100000 32 000001 1 010001 17 100001 33 000010 2 010010 18 100010 34 000011 3 010011 19 100011 35 000100 4 010100 20 100100 36 000101 5 010101 21 100101 37 000110 6 010110 22 100110 38 000111 7 010111 23 100111 39 001000 8 011000 24 101000 40 001001 9 011001 25 101001 41 001010 10 011010 26 101010 42 001011 11 011011 27 101011 43 001100 12 011100 28 101100 44 001101 13 011101 29 101101 45 001110 14 011110 30 101110 46 001111 15 011111 31 other values 46
104 11050a?pmaac?07-apr-10 AT73C246 name : inlvol access : read / write address : 0x18 76543210 inlboth inlvol table 13-41. inlvol (0x18) structure bit name description reset value 7inlboth aux / line left volume controls right channel 0: inactive 1: active. prioritary bit over inrboth. 1 6:0 inlvol aux / line input left volume selection 0000000 table 13-42. aux / line left volume selection table inlvol gain(db) inlvol gain(db) inlvol gain(db) 1011100 mute 1101101 -19 1111110 -2 1011101 -35 1101110 -18 1111111 -1 1011110 -34 1101111 -17 0000000 0 1011111 -33 11 10000 -16 0000001 1 1100000 -32 1110001 -15 0000010 2 1100001 -31 1110010 -14 0000011 3 1100010 -30 1110011 -13 0000100 4 1100011 -29 1110100 -12 0000101 5 1100100 -28 1110101 -11 0000110 6 1100101 -27 1110110 -10 0000111 7 1100110 -26 1110111 -9 0001000 8 1100111 -25 1111000 -8 0001001 9 1101000 -24 1111001 -7 0001010 10 1101001 -23 1111010 -6 0001011 11 1101010 -22 1111011 -5 >=0101111 12 1101011 -21 1111100 -4 1101100 -20 1111101 -3
105 11050a?pmaac?07-apr-10 AT73C246 name : inrvol access : read / write address : 0x19 76543210 inrboth inrvol table 13-43. inrvol (0x19) structure bit name description reset value 7 inrboth aux / line right volume controls left channel 0: inactive 1: active. 0 6:0 inrvol aux / line input right volume selection 0000000 table 13-44. aux / line right volume selection table inlvol gain(db) inlvol gain(db) inlvol gain(db) 1011100 mute 1101101 -19 1111110 -2 1011101 -35 1101110 -18 1111111 -1 1011110 -34 1101111 -17 0000000 0 1011111 -33 11 10000 -16 0000001 1 1100000 -32 1110001 -15 0000010 2 1100001 -31 1110010 -14 0000011 3 1100010 -30 1110011 -13 0000100 4 1100011 -29 1110100 -12 0000101 5 1100100 -28 1110101 -11 0000110 6 1100101 -27 1110110 -10 0000111 7 1100110 -26 1110111 -9 0001000 8 1100111 -25 1111000 -8 0001001 9 1101000 -24 1111001 -7 0001010 10 1101001 -23 1111010 -6 0001011 11 1101010 -22 1111011 -5 >=0101111 12 1101011 -21 1111100 -4 1101100 -20 1111101 -3
106 11050a?pmaac?07-apr-10 AT73C246 name : hplvol access : read / write address : 0x1a 76543210 hplvol table 13-45. hplvol (0x1a) structure bit name description reset value 7:0 hplvol headphone left volume selection 00000000 table 13-46. headphone left volume selection table hplvol gain (db) hplvol gain (db) hplvol gain (db) hplvol gain (db) 10110010 mut e 11001000 -56 11011110 -34 11110100 -12 10110011 -77 11001001 -55 11011111 -33 11110101 -11 10110100 -76 11001010 -54 11100000 -32 11110110 -10 10110101 -75 11001011 -53 11100001 -31 11110111 -9 10110110 -74 11001100 -52 11100010 -30 11111000 -8 10110111 -73 11001101 -51 11100011 -29 11111001 -7 10111000 -72 11001110 -50 11100100 -28 11111010 -6 10111001 -71 11001111 -49 11100101 -27 11111011 -5 10111010 -70 11010000 -48 11100110 -26 11111100 -4 10111011 -69 11010001 -47 11100111 -25 11111101 -3 10111100 -68 1 1010010 -46 11101000 -24 11 111110 -2 10111101 -67 11010011 -45 11101001 -23 11111111 -1 10111110 -66 11010100 -44 11101010 -22 00000000 0 10111111 -65 1 1010101 -43 11101011 -21 00000001 1 11000000 -64 11010110 -42 11101100 -20 00000010 2 11000001 -63 11010111 -41 11101101 -19 00000011 3 11000010 -62 11011000 -40 11101110 -18 00000100 4 11000011 -61 11011001 -39 11101111 -17 00000101 5 11000100 -60 11011010 -38 11110000 -16 >=00000110 6 11000101 -59 11011011 -37 11110001 -15 11000110 -58 11011100 -36 11110010 -14 11000111 -57 11011101 -35 11110011 -13
107 11050a?pmaac?07-apr-10 AT73C246 name : hprvol access : read / write address : 0x1b 76543210 hprvol table 13-47. hprvol (0x1b) structure bit name description reset value 7:0 hprvol headset right vo lume selection 00000000 table 13-48. headphone right volume selection table hprvol gain (db) hprvol gain (db) hprvol gain (db) hprvol gain (db) 10110010 mute 11001000 -56 11011110 -34 11110100 -12 10110011 -77 11001001 -55 11011111 -33 11110101 -11 10110100 -76 11001010 -54 11100000 -32 11110110 -10 10110101 -75 11001011 -53 11100001 -31 11110111 -9 10110110 -74 11001100 -52 11100010 -30 11111000 -8 10110111 -73 11001101 -51 11100011 -29 11111001 -7 10111000 -72 11001110 -50 11100100 -28 11111010 -6 10111001 -71 11001111 -49 11100101 -27 11111011 -5 10111010 -70 11010000 -48 11100110 -26 11111100 -4 10111011 -69 11010001 -47 11100111 -25 11111101 -3 10111100 -68 1 1010010 -46 11101000 -24 11 111110 -2 10111101 -67 11010011 -45 11101001 -23 11111111 -1 10111110 -66 11010100 -44 11101010 -22 00000000 0 10111111 -65 1 1010101 -43 11101011 -21 00000001 1 11000000 -64 11010110 -42 11101100 -20 00000010 2 11000001 -63 11010111 -41 11101101 -19 00000011 3 11000010 -62 11011000 -40 11101110 -18 00000100 4 11000011 -61 11011001 -39 11101111 -17 00000101 5 11000100 -60 11011010 -38 11110000 -16 >=00000110 6 11000101 -59 11011011 -37 11110001 -15 11000110 -58 11011100 -36 11110010 -14 11000111 -57 11011101 -35 11110011 -13
108 11050a?pmaac?07-apr-10 AT73C246 name : hp_control access : read / write address : 0x1c 76543210 -----hpdet_stlhpbothrhpboth table 13-49. hp_control (0x1c) structure bit name description reset value 7:3 - unused 00000 2 hpdet_st headphone plug in-out detector 0: off 1: on 0 1 lhpboth right headphone volume follows left 0: inactive 1: active. prioritary bit over rhpboth. 1 0 rhpboth left headphone volume follows right 0: inactive 1: active 0
109 11050a?pmaac?07-apr-10 AT73C246 name : audio_effects access : read / write address : 0x1d 76543210 3dfx_depth on3dfx swap_dac swap_adc mono_dac mono_adc ondeemp table 13-50. audio_effects (0x1d) structure bit name description reset value 7:6 3dfx_depth 3d effect depth control 00 5on3dfx 3d effect 0: off 1: on 0 4 swap_dac dac left / right channel swap 0: left / right inputs on left / right outputs 1: left / right inputs on right / left outputs 0 3 swap_adc adc left / right channel swap 0: left / right inputs on left / right outputs 1: left / right inputs on right / left outputs 0 2mono_dac (left + right) / 2 on left and right channels 0: inactive 1: active 0 1mono_adc left adc output on both left and right channels 0: inactive 1: active 0 0 ondeemp de-emphasis filter 0: off 1: on 0 table 13-51. 3-d effect dept h control table 3dfx_depth attenuation 00 0db 01 -6db 10 -12db 11 -18db
110 11050a?pmaac?07-apr-10 AT73C246 name : input_control access : read / write. this register is modified by audi o controller at audio path change. address : 0x1e 76543210 - linesel onmicl onmicr onadcl onadcr onlinl onlinr table 13-52. input_control (0 x1e) structure bit name description reset value 7 unused 0 6 linesel line / aux input selection 0: aux input selected 1: line input selected 1 5 onmicl left microphone amplifier 0: off 1: on 0 4 onmicr right microphone amplifier 0: off 1: on 0 3 onadcl left adc 0: off 1: on 0 2 onadcr right adc 0: off 1: on 0 1 onlinl left line input amplifier 0: off 1: on 0 0 onlinr right line input amplifier 0: off 1: on 0
111 11050a?pmaac?07-apr-10 AT73C246 name : output_control access : read / write this register is modified by audi o controller at audio path change. address : 0x1f 76 5 43210 - onsidetone onplayback onbypass onhpl onhpr ondacl ondacr table 13-53. output_control (0x1f) structure bit name description reset value 7 unused 0 6 onsidetone sidetone switch 0: muted 1: enabled 0 5 onplayback playback switch 0: muted 1: enabled 0 4 onbypass bypass switch 0: muted 1: enabled 0 3 onhpl left headphone amplifier 0: off 1: on 0 2 onhpr right headphone amplifier 0: off 1: on 0 1 ondacl left dac 0: off 1: on 0 0 ondacr right dac 0: off 1: on 0
112 11050a?pmaac?07-apr-10 AT73C246 name : input_mixer access : read / write this register is modified by audi o controller at audio path change. address : 0x20 76543210 - - mixmicl mixmicr mixlinel mixliner onmixl onmixr table 13-54. input_mixer (0x20) structure bit name description reset value 7:6 - unused 00 5mixmicl left microphone input mixer switch 0: muted 1: enabled 0 4mixmicr right microphone input mixer switch 0: muted 1: enabled 0 3mixlinel left line / aux input mixer switch 0: muted 1: enabled 0 2mixliner right line / aux input mixer switch 0: muted 1: enabled 0 1onmixl left input mixer on / off 0: muted 1: enabled 0 0onmixr right input mixer on / off 0: muted 1: enabled 0
113 11050a?pmaac?07-apr-10 AT73C246 name : sidetone_vol access : read / write address : 0x21 76543210 - - - sidetone_vol table 13-55. sidetone_vol (0x21) structure bit name description reset value 7:5 unused 000 4:0 sidetone_vol left / right sidetone path attenuation 01011 table 13-56. left / right sidetone path attenuation selection table sidetone_vol att(db) sidetone_vol att(db) sidetone_vol att(db) 00000 0 00100 12 01000 24 00001 3 00101 15 01001 27 00010 6 00110 18 01010 30 00011 9 00111 21 >=01011 30
114 11050a?pmaac?07-apr-10 AT73C246 name : equalizer access : read / write address : 0x22 76543210 ---- eq_sel table 13-57. equalizer (0x22) structure bit name description reset value 7:4 0 3:0 eq_sel equalizer selection 0000 table 13-58. equalizer selection table(0x22) structure eq_sel description 0000 flat response 0001 bass boost +12db 0010 bass boost +6db 0011 bass cut -12db 0100 bass cut -6db 0101 medium boost +3db 0110 medium boost +8db 0111 medium cut -3db 1000 medium cut -8db 1001 treble boost +12db 1010 treble boost +6db 1011 treble cut -12db 1100 treble cut -6db other value flat response.
115 11050a?pmaac?07-apr-10 AT73C246 name : adc_ctrl access : read / write address : 0x30 76543210 on_adc on_buf - - - ts table 13-59. adc_ctrl (0x30) structure bit name description reset value 7on_adc adc function 0: off 1: on 0 6on_buf analog buffer 0: off 1: on 0 5:3 unused - 000 2:0 ts sampling period 000 table 13-60. adc sampling period selection table ts sampling period (s) 000 0.01 001 0.02 010 0.1 011 1 100 2 101 3 110 4 111 max speed
116 11050a?pmaac?07-apr-10 AT73C246 name : adc_mux_1 access : read / write address : 0x31 76543210 - vin - vdd4 vdd3 vdd2 vdd1 vdd0 table 13-61. adc_mux1 (0x3 1) structure bit name description reset value 7 unused - 0 6vin vin channel selection 0: not selected 1: selected 1 5 unused - 1 4 vdd4 vdd4 channel selection 0: not selected 1: selected 1 3 vdd3 vdd3 channel selection 0: not selected 1: selected 1 2 vdd2 vdd2 channel selection 0: not selected 1: selected 1 1 vdd1 vdd1 channel selection 0: not selected 1: selected 1 0 vdd0 vdd0 channel selection 0: not selected 1: selected 1
117 11050a?pmaac?07-apr-10 AT73C246 name : adc_mux_2 access : read / write address : 0x32 76543210 ----ana3ana2ana1ana0 table 13-62. adc_mux2 (0x3 2) structure bit name description reset value 7:4 unused - 0000 3ana3 ana3 channel selection 0: not selected 1: selected 1 2ana2 ana2 channel selection 0: not selected 1: selected 1 1ana1 ana1 channel selection 0: not selected 1: selected 1 0ana0 ana0 channel selection 0: not selected 1: selected 1
118 11050a?pmaac?07-apr-10 AT73C246 name : adc_ana0_msb access : read only address : 0x33 name : adc_ana0_lsb access : read only address : 0x34 76543210 adc<9:2> table 13-63. adc_ana0_msb (0x3 3) structure bit name description reset value 7:0 adc<9:2> adc_out<9:2> for ana0 channel 00000000 76543210 adc<1:0> table 13-64. adc_ana0_lsb (0x34) structure bit name description reset value 7:2 - unused 1:0 adc<1:0> adc_out<1:0> for ana0 channel 00
119 11050a?pmaac?07-apr-10 AT73C246 name : adc_ana1_msb access : read only address : 0x35 name : adc_ana1_lsb access : read only address : 0x36 76543210 adc<9:2> table 13-65. adc_ana1_msb (0x3 5) structure bit name description reset value 7:0 adc<9:2> adc_out<9:2> for ana1 channel 00000000 76543210 adc<1:0> table 13-66. adc_ana1_lsb (0x36) structure bit name description reset value 7:2 - unused 1:0 adc<1:0> adc_out<1:0> for ana1 channel 00
120 11050a?pmaac?07-apr-10 AT73C246 name : adc_ana2_msb access : read only address : 0x37 name : adc_ana2_lsb access : read only address : 0x38 76543210 adc<9:2> table 13-67. adc_ana2_msb (0x3 7) structure bit name description reset value 7:0 adc<9:2> adc_out<9:2> for ana2 channel 00000000 76543210 adc<1:0> table 13-68. adc_ana2_lsb (0x38) structure bit name description reset value 7:2 - unused 1:0 adc<1:0> adc_out<1:0> for ana2 channel 00
121 11050a?pmaac?07-apr-10 AT73C246 name : adc_ana3_msb access : read only address : 0x39 name : adc_ana3_lsb access : read only address : 0x3a 76543210 adc<9:2> table 13-69. adc_ana3_msb (0x3 9) structure bit name description reset value 7:0 adc<9:2> adc_out<9:2> for ana3 channel 00000000 76543210 adc<1:0> table 13-70. adc_ana3_lsb (0x3 a) structure bit name description reset value 7:2 - unused 1:0 adc<1:0> adc_out<1:0> for ana3 channel 00
122 11050a?pmaac?07-apr-10 AT73C246 name : adc_vdd0_msb access : read only address : 0x3b name : adc_vdd0_lsb access : read only address : 0x3c 76543210 adc<9:2> table 13-71. adc_vdd0_msb (0x3b) structure bit name description reset value 7:0 adc<9:2> adc_out<9:2> for vdd0 channel 00000000 76543210 adc<1:0> table 13-72. adc_vdd0_lsb (0x3c) structure bit name description reset value 7:2 - unused 1:0 adc<1:0> adc_out<1:0> for vdd0 channel 00
123 11050a?pmaac?07-apr-10 AT73C246 name : adc_vdd1_msb access : read only address : 0x3d name : adc_vdd1_lsb access : read only address : 0x3e 76543210 adc<9:2> table 13-73. adc_vdd1_msb (0x3d) structure bit name description reset value 7:0 adc<9:2> adc_out<9:2> for vdd1 channel 00000000 76543210 adc<1:0> table 13-74. adc_vdd1_lsb (0x3e) structure bit name description reset value 7:2 - unused 1:0 adc<1:0> adc_out<1:0> for vdd1 channel 00
124 11050a?pmaac?07-apr-10 AT73C246 name : adc_vdd2_msb access : read only address : 0x3f name : adc_vdd2_lsb access : read only address : 0x40 76543210 adc<9:2> table 13-75. adc_vdd2_msb (0x3f) structure bit name description reset value 7:0 adc<9:2> adc_out<9:2> for vdd2 channel 00000000 76543210 adc<1:0> table 13-76. adc_vdd2_lsb (0x4 0) structure bit name description reset value 7:2 - unused 1:0 adc<1:0> adc_out<1:0> for vdd2 channel 00
125 11050a?pmaac?07-apr-10 AT73C246 name : adc_vdd3_msb access : read only address : 0x41 name : adc_vdd3_lsb access : read only address : 0x42 76543210 adc<9:2> table 13-77. adc_vdd3_msb (0x41) structure bit name description reset value 7:2 adc<9:2> adc_out<9:2> for vdd3 channel 00000000 76543210 adc<1:0> table 13-78. adc_vdd3_lsb (0x4 2) structure bit name description reset value 7:2 - unused 1:0 adc<1:0> adc_out<1:0> for vdd3 channel 00
126 11050a?pmaac?07-apr-10 AT73C246 name : adc_vdd4_msb access : read only address : 0x43 name : adc_vdd4_lsb access : read only address : 0x44 76543210 adc<9:2> table 13-79. adc_vdd4_msb (0x43) structure bit name description reset value 7:0 adc<9:2> adc_out<9:2> for vdd4 channel 00000000 76543210 adc<1:0> table 13-80. adc_vdd4_lsb (0x4 4) structure bit name description reset value 7:2 - unused 1:0 adc<1:0> adc_out<1:0> for vdd4 channel 00
127 11050a?pmaac?07-apr-10 AT73C246 name : adc_vin_msb access : read only address : 0x47 name : adc_vin_lsb access : read only address : 0x48 76543210 adc<9:2> table 13-81. adc_vin_msb (0x47) structure bit name description reset value 7:0 adc<9:2> adc_out<9:2> for vin channel 00000000 76543210 adc<1:0> table 13-82. adc_vin_lsb (0x4 8) structure bit name description reset value 7:2 - unused 1:0 adc<1:0> adc_out<1:0> for vin channel 00
128 11050a?pmaac?07-apr-10 AT73C246 name : adc_ana_lsb access : read only address : 0x49 name : rtc_ctrl access : read / write address : 0x50 76543210 adc_ana3<1:0> adc_ana2<1:0> adc_ana1<1:0> adc_ana0<1:0> table 13-83. adc_ana_lsb (0x49) structure bit name description reset value 7:6 adc_ana3<1:0> adc_out<1:0:> for ana3 channel 00 5:4 adc_ana2<1:0> adc_out<1:0:> for ana2 channel 00 3:2 adc_ana1<1:0> adc_out<1:0:> for ana1 channel 00 1:0 adc_ana0<1:0> adc_out<1:0:> for ana0 channel 00 76543210 - - rtc_write rtc_sel rtc_en table 13-84. rtc_ctrl (0x50) structure bit name description reset value 7:3 - unused 2rtc_write rtc read/write: rtc_write = 0: read mode rtc_write = 1: write mode 0 1 rtc_sel rtc block select: rtc_sel = 0: not selected rtc_sel = 1: selected 0 0rtc_en rtc block enable: rtc_en = 0: disabled rtc_en = 1: enabled 0
129 11050a?pmaac?07-apr-10 AT73C246 name : rtc_addr access : read / write address : 0x51 name : rtc_data0 access : read / write address : 0x52 76543210 rtc_addr table 13-85. rtc_addr (0x51) structure bit name description reset value 7:0 rtc_addr rtc address 0000 76543210 rtc_data0 table 13-86. rtc_data0 (0x52) structure bit name description reset value 7:0 rtc_data0 rtc data 0 0000000
130 11050a?pmaac?07-apr-10 AT73C246 name : rtc_data1 access : read / write address : 0x53 name : rtc_data2 access : read / write address : 0x54 name : rtc_data3 access : read / write address : 0x55 76543210 rtc_data1 table 13-87. rtc_data1 (0x53) structure bit name description reset value 7:0 rtc_data1 rtc data 1 0000000 76543210 rtc_data2 table 13-88. rtc_data2 (0x54) structure bit name description reset value 7:0 rtc_data2 rtc data 2 0000000 76543210 rtc_data3 table 13-89. rtc_data3 (0x55) structure bit name description reset value 7:0 rtc_data3 rtc data 3 0000000
131 11050a?pmaac?07-apr-10 AT73C246 name : backup_ctrl access : read / write address : 0x56 name : version access : read address : 0x7f 76543210 ----osc_updtosc_enosc_statrst_bkup table 13-90. backup_ctrl (0x 56) structure bit name description reset value 7:4 - unused 0000 3 osc_updt rtc oscillator update 0: no action. 1: update rtc oscillator with osc_en 0 2osc_en rtc oscillator enable request 0: oscillator off. 1: oscillator on. 0 1osc_stat rtc oscillator status (read only) 0: oscillator off. 1: oscillator on. 0 0 rst_bkup reset of the backup area 0: backup area active 1: backup area in reset state 0 76543210 software_tag version table 13-91. version (0x7f) structure bit name description reset value 7:4 software_tag software tag to identify product specificities as described in section 17. ?ordering information? on page 154 . xxxx 3:0 version ?0001?: rev. c samples ?0010?: rev. d samples xxxx
132 11050a?pmaac?07-apr-10 AT73C246 14. pmu and audio soft control: quick start 14.1 rtc examples 14.1.1 rtc oscillator power-on // set osc_en = 1 and osc_updt = 1 twi_write 0x0c @backup_ctrl // wait > 200us. wait 200us // set osc_updt = 0 twi_write 0x04 @backup_ctrl // read backup_ctrl to verify osc_stat bit. result = 0x06. twi_read @backup_ctrl 14.1.2 rtc oscillator power-off // set osc_en = 0 and osc_updt = 1 twi_write 0x08 @backup_ctrl // wait 200us wait 200us // set osc_updt = 0 twi_write 0x00 @backup_ctrl // read backup_ctrl to verify osc_stat bit. result = 0x00. twi_read @backup_ctrl 14.1.3 rtc domain reset // set rst_bkup = 1 twi_write 0x01 @backup_ctrl // wait 200s wait 200us // set rst_bkup = 0 twi_write 0x00 @backup_ctrl note: reset of the rtc domain powers off the rtc oscillator. 14.1.4 rtc write operation the following example makes a generic 32-bit wr ite operation into the rtc macro. the 32-bit data is split into 4 bytes, that are successively sent over the twi. unsigned int rtc_data; char data0 = (char) (rtc_data); // lsbs char data1 = (char) (rtc_data >> 8); char data2 = (char) (rtc_data >> 16); char data3 = (char) (rtc_data >> 24); // msbs // select rtc_addr = addr. addr is the rtc macro register to write, twi_write addr @rtc_addr // set rtc_data0 to rtc_data4 registers. twi_write data0 @rtc_data0 twi_write data1 @rtc_data1
133 11050a?pmaac?07-apr-10 AT73C246 twi_write data2 @rtc_data2 twi_write data3 @rtc_data3 // set rtc_write = 1 (write) and rtc_sel = 1 twi_write 0x06 @ rtc_ctrl // pulse rtc_en twi_write 0x07 @ rtc_ctrl twi_write 0x06 @ rtc_ctrl // disable rtc access twi_write 0x00 @ rtc_ctrl 14.1.5 rtc read operation the following example makes a generic 32-bit read operation into the rtc macro. the 32-bit rtc data is split into 4 bytes, that are successively read over the twi. // select rtc_addr = addr. addr is the rtc macro register to read, twi_write addr @rtc_addr // set rtc_write = 0 (read) and rtc_sel = 1 twi_write 0x02 @ rtc_ctrl // pulse rtc_en twi_write 0x03 @ rtc_ctrl twi_write 0x02 @ rtc_ctrl // read rtc_data0 to rtc_data4 registers. twi_read @rtc_data0 // lsbs twi_read @rtc_data1 twi_read @rtc_data2 twi_read @rtc_data3 // msbs // disable rtc access twi_write 0x00 @ rtc_ctrl 14.1.6 rtc date and time update in the following example, the rtc date and time is set to ?12 october 2004, 08h 49min 59s?. the write_rtc and read_rtc functions operate as described in the previous sections. // disable rtc interrupt mask twi_write 0xfe @pmu_mask // enable rtc ackupd it @rtc_ier (rtc_addr 0x20). write_rtc 0x00000001 @rtc_ier // set updtime and updcal @rtc_cr (rtc_addr 0x00). write_rtc 0x00000003 @rtc_cr // wait itb low. this ensures that the rtc is ready to be updated. // reset it by read operation, result is 0x01. twi_read @pmu_it // read in rtc_sr that ackupd = 1 (rtc_addr = 0x18) read_rtc @rtc_sr // disable ackupd it @rtc_idr (rtc_addr = 0x24) write_rtc 0x00000001 @rtc_idr // write date @rtc_calr (rtc_addr = 0x0c) (12 october 2004) write_rtc 0x12300420 @rtc_calr
134 11050a?pmaac?07-apr-10 AT73C246 // write time @rtc_timr (rtc_addr = 0x08) (08h 49min 59s) write_rtc 0x00084959 @rtc_timr // start rtc @rtc_cr (rtc_addr = 0x00) write_rtc 0x00000000 @rtc_cr 14.2 audio examples 14.2.1 basic audio codec setting using automatic path control the following example demonstrates an automat ic audio path setting. assuming that the audio codec is supplied by the ldo4, the sequence is the following: ? make the codec interface configuration, ? set the digital-in to headphone-out path, ? put the audio codec in standby mode, ? release the standby mode to re-activate the selected path, ? change the path on-the-fly, ? shutdown the codec. // start ldo4 @3.3v twi_write 0x8c @ vdd4_ctrl // digital audio interface configuration // master clock = 12.288mhz, master / slave = slave. // dai mode = i2s mode, word length = 24 bits, fs = 48khz twi_write 0x01 @ dai_control twi_write 0x63 @ frame_control // analog interface configuration // mic. config: l & r single ended, micbias = off, mic. detection = off. // headphone config: ac coupled, // automatic soft ramping = on, asr timing = 11 (~10ms / step) twi_write 0x00 @ mic_control twi_write 0x27 @ audio_control // analog gain // headphone (l & r) gain: -20db. (lhpboth set by default in hp_control) // mic l & r gain: +26 db. // unmute all gains. no power-up is performed. twi_write 0xec @ hplvol twi_write 0x1a @ miclvol twi_write 0x1a @ micrvol twi_write 0x00 @ mute // audio start // enac = 1, standby = 1. path = 1 (dac playback) // at the first start, vmid capacitor is charged.
135 11050a?pmaac?07-apr-10 AT73C246 // wait (3.tau) = 300ms with 1uf before standby release. (vmid will be // discharged only when enac = 0.) // from this point audio data can be sent over the digital audio interface. twi_write 0x61 @ autostart. wait 300ms // release standby. the audio codec starts silently, the gains are slowly // ramped up from mute to the register gains. the codec is active. twi_write 0x41 @ autostart // codec pause by standby // all gains are softly ramped down to mute. the codec functions are // shut down. current consumption is reduced to a few hundreds of micro- // amps. vmid remains charged twi_write 0x61 @ autostart // pause out: standby release. the codec softly re-starts. twi_write 0x41 @ autostart // on-the-fly path change // path = 19: digital in to headphone out + mic in to digital out. // the codec controller powers up automatically the new path. the dac // playback is not affected by starting the mic. recording. twi_write 0x52 @ autostart // codec shutdown. enac = 0, standby = 1. the codec turns off smoothly. // in case of ac coupling output configuration, hpr & hpl will slowly // discharge following vmid time constant. twi_write 0x20 @ autostart wait 600ms // disable dcblock bit. twi_write 0x07 @ audio_control // ldo4 shutdown. twi_write 0x0c @ vdd4_control 14.2.2 basic audio codec setting using custom path control the following example demonstrates a custom audio path setting. assuming that the audio codec is supplied by the ldo4, the sequence is the following: ? make the codec analog and digital interfaces configuration, ? enter the custom path mode and configure a path with dac input and headphone amplifier output, ? put the audio codec in standby mode, ? release the standby mode to re-activate the selected path, ? change the path on-the-fly to add the microphone inputs to the dac signal, ? shutdown the codec.
136 11050a?pmaac?07-apr-10 AT73C246 // start ldo4 @3.3v twi_write 0x8c @ vdd4_ctrl // digital audio interface configuration // master clock = 12.288mhz, master / slave = slave. // dai mode = i2s mode, word length = 24 bits, fs = 48khz twi_write 0x01 @ dai_control twi_write 0x63 @ frame_control // analog interface configuration // mic. config: l & r single ended, micbias = off, mic. detection = off. // headphone config: ac coupled, // automatic soft ramping = on, asr timing = 11 (~10ms / step) twi_write 0x00 @ mic_control twi_write 0x27 @ audio_control // analog gain // headphone (l & r) gain: -20db. (lhpboth set by default in hp_control) // mic l & r gain: +26 db. // unmute all gains. no power-up is performed. twi_write 0xec @ hplvol twi_write 0x1a @ miclvol twi_write 0x1a @ micrvol twi_write 0x00 @ mute // enter the custom path configuration mode twi_write 0x2f @ audio_control // audio start // enac = 1, standby = 1. path = 0 (not read by the audio controller) // at the first start, vmid capacitor is charged. // wait (3.tau) = 300ms with 1uf before standby release. (vmid will be // discharged only when enac = 0.) // from this point audio data can be sent over the digital audio interface. twi_write 0x60 @ autostart. wait 300ms // audio path definition: dac input to headphone output. the software sets // the bits: ondacl, ondacr, onhpl, onhpr and playback by writing // the registers input_control, output_control, and input_mixer. // the changes are not taken immediately into account (enconf = 0). twi_write 0x40 @ input_ctrl twi_write 0x2f @ output_ctrl twi_write 0x00 @ input_mixer // enconf pulse: the audio controller takes the requested changes into
137 11050a?pmaac?07-apr-10 AT73C246 // account. twi_write 0x3f @ audio_control twi_write 0x2f @ audio_control // standby release. the codec softly starts. twi_write 0x40 @ autostart. // codec pause by standby // all gains are softly ramped down to mute. the codec functions are // shut down. current consumption is reduced to a few hundreds of micro- // amps. vmid remains charged twi_write 0x60 @ autostart // pause out: standby release. the codec softly re-starts. twi_write 0x40 @ autostart // on-the-fly path change: the stereo microphone inputs are added to the // dac playback. the software sets: onmicl, onmicr, and onsidetone. twi_write 0x70 @ input_ctrl twi_write 0x6f @ output_ctrl twi_write 0x00 @ input_mixer // sidetone gain twi_write 0x00 @ sidetone_vol // enconf pulse: the audio controller takes the requested changes into // account. the path modification is here immediate because standby=0. twi_write 0x3f @ audio_control twi_write 0x2f @ audio_control // codec shutdown. enac = 0, standby = 1. the codec turns off smoothly. // in case of ac coupling output configuration, hpr & hpl will slowly // discharge following vmid time constant. twi_write 0x20 @ autostart wait 600ms // disable dcblock bit. twi_write 0x07 @ audio_control // ldo4 shutdown. twi_write 0x0c @ vdd4_control
138 11050a?pmaac?07-apr-10 AT73C246
139 11050a?pmaac?07-apr-10 AT73C246 15. typical performance characteristics 15.1 pmu: power supply sequences figure 15-1. powerdown state to run state supplies start-up figure 15-2. run sate to powerdown state supplies shut-down powerdown to run s tate s equence a powerdown to run s tate s equence b run to powerdown s tate s equence a run to powerdown s tate s equence b
140 11050a?pmaac?07-apr-10 AT73C246 figure 15-3. detailed supplies start-up figure 15-4. detailed supplies shutdown detailed s upplies s tart-up s equence a detailed s upplies s tart-up s equence b detailed s upplies s hutdown s equence a detailed s upplies shutdown s equence b
141 11050a?pmaac?07-apr-10 AT73C246 figure 15-5. run state to standby state figure 15-6. standby to run state run to s tandby s tate (default setting) s equence a run to s tandby s tate (default setting) s equence b s tandby to run s tate (default setting) s equence a s tandby to run s tate (default setting) s equence b
142 11050a?pmaac?07-apr-10 AT73C246 15.2 dcdc0 and dcdc1 unless otherwise noted, the reported meas urement were performed at room temperature. external components are those described in section 5. ?application block diagram? on page 8 . figure 15-7. dcdc0 transient load regulation performance dcdc0 - vin = 3 . 3 v - vout = 1. 8 5v load s tep 0 to 600ma / 1us dcdc0 - vin = 3 . 3 v - vout = 1. 8 5v load s tep 600 to 0ma / 1us dcdc0 - vin = 5.5v - vout = 1. 8 5v load s tep 0 to 600ma / 1us dcdc0 - vin = 5.5v - vout = 1. 8 5v load s tep 600 to 0ma / 1us
143 11050a?pmaac?07-apr-10 AT73C246 figure 15-8. dcdc0 ripple and efficency performance dcdc0 - vout = 1. 8 v efficiency in pfm and pwm modes dcdc0 - vin = 5.5v - vout = 1. 8 v output voltage ripple
144 11050a?pmaac?07-apr-10 AT73C246 figure 15-9. dcdc1transient load regulation performance dcdc0 - vin = 3 . 3 v - vout = 1.2v load s tep 0 to 600ma / 1us dcdc0 - vin = 3 . 3 v - vout = 1.2v load s tep 600 to 0ma / 1us dcdc0 - vin = 5.5v - vout = 1.2v load s tep 0 to 600ma / 1us dcdc0 - vin = 5.5v - vout = 1.2v load s tep 600 to 0ma / 1us
145 11050a?pmaac?07-apr-10 AT73C246 figure 15-10. dcdc0 ripple and efficiency performance dcdc1 - vout = 1.2v efficiency in pfm and pwm modes dcdc1 - vin = 5.5v - vout = 1.2v output voltage ripple
146 11050a?pmaac?07-apr-10 AT73C246 15.3 ldo2 unless otherwise noted, the reported meas urement were performed at room temperature. external components are those described in section 5. ?application block diagram? on page 8 . figure 15-11. ldo2 tansient and static load regulation performance ldo2- vin = 1. 8 v - vout = 1v load s tep 0 to 3 00ma / 1us ldo2 - vin = 1. 8 v - vout = 1v load s tep 3 00 to 0ma / 1us ldo2 - vin = 1. 8 v - vout = 1v s tatic load regulation - 0 to 3 00ma ldo2 - vin = 1.7v - vout = 1.2v s tatic load regulation - 0 to 3 00ma
147 11050a?pmaac?07-apr-10 AT73C246 15.4 ldo3 unless otherwise noted, the reported meas urement were performed at room temperature. external components are those described in section 5. ?application block diagram? on page 8 . figure 15-12. ldo3 transient and static load regulation performance ldo 3 - vin = 5.5v - vdd 3 = 3 . 3 v load s tep 0 to 200ma / 1us ldo 3 - vin = 5.5v - vdd 3 = 3 . 3 v load s tep 200 to 0ma / 1us ldo 3 - vin = 3 .6v - vdd 3 = 3 . 3 v s tatic load regulation - 0 to 200ma ldo 3 - vdd 3 = 3 . 3 v - 200ma output load drop out characteristic. (vdd 3 reg = vdd 3 with vin 3 > vdd 3 + 3 00mv)
148 11050a?pmaac?07-apr-10 AT73C246 15.5 audio unless otherwise noted, the reported measurement were pe rformed at room temperature with avdd = 3.3v supplied from ldo4. typical components as described in section 5. ?application block diagram? on page 8 are used. figure 15-13. microphone recording waveforms dierential microphone recording ( path 5) -1dbv / 1khz input - fs = 48khz - 16kpts fft dierential microphone recording ( path 5) -60dbv / 1khz input - fs = 48khz - 16kpts fft dierential microphone recording ( path 5) thd+n ratio versus input level
149 11050a?pmaac?07-apr-10 AT73C246 figure 15-14. dac playback waveforms dac playback ( path 1) - load 10k 0 dbfs / 1khz input - fs = 48khz - 32kpts fft dac playback ( path 1) - load 10k -60 dbfs / 1khz input - fs = 48khz - 32kpts fft dac playback ( path 1) - load 10k thd+n ratio versus input level dac playback ( path 1) - load 32 ohms ac coupled 20mw ouput power - fs = 48khz - 32kpts fft
150 11050a?pmaac?07-apr-10 AT73C246 figure 15-15. line record waveforms line record (path 7) -1 dbv / 1khz input - fs = 48khz - 32kpts fft line record (path 7) -60 dbv / 1khz input - fs = 48khz - 32kpts fft line record (path 7) thd+n ratio versus input level
151 11050a?pmaac?07-apr-10 AT73C246 figure 15-16. line bypass waveforms line bypass (path 5) 0 dbv / 1khz input - 10k load - 16kpts fft line bypass (path 5) -60 dbv / 1khz input - 10k load - 16kpts fft line record (path 5) - 10k load thd+n ratio versus input level
152 11050a?pmaac?07-apr-10 AT73C246
153 11050a?pmaac?07-apr-10 AT73C246 16. package information figure 16-1. mechanical package drawing for 64-lead quad flat no lead package
154 11050a?pmaac?07-apr-10 AT73C246 17. ordering information notes: 1. see ?version? (0x7f) register definition. 2. see ?power manager state description? on page 29 and ?typical performance characteristics? on page 139 . table 17-1. ordering information ordering code and marking package temperature operating range supplies default values power sequence type (2) software tag (1) AT73C246 qfn64 7.5 x7.5mm green -40c to +85c vdd0 = 1.85v vdd1 = 1.20v vdd2 = 1.00v vdd3 = 3.30v vdd4 = 3.30v a0000 AT73C246-a qfn64 7.5 x7.5mm green -40c to +85c vdd0 = 1.80v vdd1 = 1.20v vdd2 = 1.20v vdd3 = 3.30v vdd4 = 3.30v b0001 AT73C246-b qfn64 7.5 x7.5mm green -40c to +85c vdd0 = 1.80v vdd1 = 1.00v vdd2 = 1.00v vdd3 = 3.30v vdd4 = 3.30v b0010
155 11050a?pmaac?07-apr-10 AT73C246 18. revision history table 18-1. revision history doc. rev date comments change request ref. 11050a 07-apr-10 first issue
156 11050a?pmaac?07-apr-10 AT73C246
i 11050a?pmaac?07-apr-10 AT73C246 1 description ............ .............. .............. .............. .............. .............. ............. 2 2 block diagram ............ ................ ................. ................ ................ ............. 3 3 package and pinout ............ .............. .............. .............. .............. ............. 4 4 pin description ......... ................ ................ ................. ................ ............... 5 5 application block diagram ..... ................ ................. ................ ............... 8 6 absolute maximum ratings .... ................ ................. ................ ............. 11 7 recommended operating condi tions .............. .............. .............. ........ 11 8 power dissipation ratings . .............. .............. .............. .............. ........... 11 9 pmu electrical characteristics ............... ................. ................ ............. 12 9.1current consumption versus modes ......................................................................12 9.2supply monitor thresholds ......................................................................................12 9.3digital i/os dc characteristics ................................................................................13 9.4dcdc0 and dcdc1 ................................................................................................14 9.5ldo2 ....................................................................................................................... 16 9.6ldo3 ....................................................................................................................... 17 9.7ldo4 ....................................................................................................................... 18 9.8ldo5 ....................................................................................................................... 19 9.9measurement bridge and 10-bit adc .....................................................................20 9.10rtc crystal oscillator ........................... ................................................................21 9.11die temperature sensor ....................... ................................................................21 10 audio codec electrical char acteristics ........ .............. .............. ........... 22 11 pmu functional description .. ................. ................. ................ ............. 25 11.1power manager state diagram ................ .............................................................25 11.2pmu startup and shutdown state diagra m ..........................................................26 11.3power manager cond itional transitions ................................................................27 11.4power manager state description .........................................................................29 11.5dcdc0 and dcdc1 functional descriptio n .........................................................36 11.6ldo2 functional description .................................................................................37 11.7ldo3 and ldo4 functional description ...............................................................37 11.8power fail detector s .............................................................................................38 11.9measurement bridge and 10-bit adc .... ................................................................38 11.10real time clock (rtc) user interface ................................................................40 11.11die temperature sensor ..................... ................................................................54
ii 11050a?pmaac?07-apr-10 AT73C246 12 audio codec functional description ........ ................ ................ ........... 55 12.1description .............................................................................................................55 12.2audio codec block diagram ..................................................................................55 12.3audio codec controls ............................................................................................56 12.4audio controller .....................................................................................................57 12.5audio codec power consumption versus programmed audio path ....................63 12.6digital audio interface ...........................................................................................66 12.7digital filters transfer function .............................................................................68 12.8analog audio interfaces ........................................................................................74 13 two wire interface and control registers ................ ................ ........... 77 13.1two-wire interface (twi) protocol ..... ....................................................................77 13.2pmu register tables ............................................................................................79 14 pmu and audio soft control: quick star t .............. ................ ........... 132 14.1rtc examples ....................................................................................................132 14.2audio examples ...................................................................................................134 15 typical performance charac teristics ................... ................. ............. 139 15.1pmu: power supply sequ ences .........................................................................139 15.2dcdc0 and dcdc1 ............................................................................................142 15.3ldo2 ...................................................................................................................146 15.4ldo3 ...................................................................................................................147 15.5audio .................................................................................................................148 16 package information ........... .............. .............. .............. .............. ......... 153 17 ordering information .......... .............. .............. .............. .............. ......... 154 18 revision history ................ .............. .............. .............. .............. ........... 155
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